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Message-ID: <95aaafe2-a362-4f55-9d38-c0d2dcb21cf0@kernel.org>
Date: Wed, 12 Nov 2025 12:41:24 -0600
From: Dinh Nguyen <dinguyen@...nel.org>
To: niravkumarlaxmidas.rabara@...era.com, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 2/2] arm64: dts: socfpga: add Agilex3 board
On 11/12/25 04:56, niravkumarlaxmidas.rabara@...era.com wrote:
> From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@...era.com>
>
> Agilex3 SoCFPGA development kit is a small form factor board similar to
> Agilex5 013b board.
> Agilex3 SoCFPGA is derived from Agilex5 SoCFPGA, with the main difference
> of CPU cores — Agilex3 has 2 cores compared to 4 in Agilex5.
Please fix up the message's formatting a bit. I don't think you need the
additional newline.
>
> Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@...era.com>
> ---
> v3 change:
> - Add agilex5 fallback compatible string.
>
> v2 link:
> https://lore.kernel.org/all/97fea9a15bfe2a3d52d5b75bee6bda25615422e7.1762840092.git.niravkumarlaxmidas.rabara@altera.com/
>
> v2 changes:
> - Use separate dtsi file for agilex3 instead of using agilex5 dtsi.
>
> v1 link:
> https://lore.kernel.org/all/aa19e005a2aa2aab63c8fe8cbaee7f59c416690f.1762756191.git.niravkumarlaxmidas.rabara@altera.com/
>
> arch/arm64/boot/dts/intel/Makefile | 1 +
> .../arm64/boot/dts/intel/socfpga_agilex3.dtsi | 17 +++
> .../boot/dts/intel/socfpga_agilex3_socdk.dts | 127 ++++++++++++++++++
> 3 files changed, 145 insertions(+)
> create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex3.dtsi
> create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
>
> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
> index 391d5cbe50b3..a117268267ee 100644
> --- a/arch/arm64/boot/dts/intel/Makefile
> +++ b/arch/arm64/boot/dts/intel/Makefile
> @@ -2,6 +2,7 @@
> dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
> socfpga_agilex_socdk.dtb \
> socfpga_agilex_socdk_nand.dtb \
> + socfpga_agilex3_socdk.dtb \
> socfpga_agilex5_socdk.dtb \
> socfpga_agilex5_socdk_013b.dtb \
> socfpga_agilex5_socdk_nand.dtb \
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex3.dtsi
> new file mode 100644
> index 000000000000..4e55513d93c4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3.dtsi
> @@ -0,0 +1,17 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2025, Altera Corporation
> + */
> +
> +/dts-v1/;
> +#include "socfpga_agilex5.dtsi"
> +
> +/ {
> + compatible = "intel,socfpga-agilex3", "intel,socfpga-agilex5";
> +
> +/* Agilex3 has only 2 CPUs */
> +&{/cpus} {
> + /delete-node/ cpu@2;
> + /delete-node/ cpu@3;
>
There's no need for another dtsi if you're referencing the Agilex5 dtsi.
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
> new file mode 100644
> index 000000000000..76efaac82e27
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
> @@ -0,0 +1,127 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2025, Altera Corporation
> + */
> +#include "socfpga_agilex3.dtsi"
Include socfpga_agilex5.dtsi here.
> +
> +/ {
> + model = "SoCFPGA Agilex3 SoCDK";
> + compatible = "intel,socfpga-agilex3-socdk", "intel,socfpga-agilex3",
> + "intel,socfpga-agilex5";
> +
> + aliases {
> + serial0 = &uart0;
> + ethernet2 = &gmac2;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
Just add this here:
+ cpus {
+ /delete-node/ cpu@2;
+ /delete-node/ cpu@3;
+ };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led0 {
> + label = "hps_led0";
> + gpios = <&porta 1 GPIO_ACTIVE_HIGH>;
> + };
> +
> + led1 {
> + label = "hps_led1";
> + gpios = <&porta 12 GPIO_ACTIVE_HIGH>;
> + };
> +
> + };
> +
> + memory@...00000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the reg */
> + reg = <0x0 0x80000000 0x0 0x0>;
> + };
> +};
> +
> +&gmac2 {
> + status = "okay";
> + phy-mode = "rgmii-id";
> + phy-handle = <&emac2_phy0>;
> + max-frame-size = <9000>;
> +
> + mdio0 {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + emac2_phy0: ethernet-phy@0 {
> + reg = <0>;
> + rxc-skew-ps = <0>;
> + rxdv-skew-ps = <0>;
> + rxd0-skew-ps = <0>;
> + rxd1-skew-ps = <0>;
> + rxd2-skew-ps = <0>;
> + rxd3-skew-ps = <0>;
> + txc-skew-ps = <0>;
> + txen-skew-ps = <60>;
> + txd0-skew-ps = <60>;
> + txd1-skew-ps = <60>;
> + txd2-skew-ps = <60>;
> + txd3-skew-ps = <60>;
> + };
> + };
> +};
> +
> +&gpio0 {
> + status = "okay";
> +};
> +
> +&gpio1 {
> + status = "okay";
> +};
> +
> +&osc1 {
> + clock-frequency = <25000000>;
> +};
> +
> +&qspi {
> + status = "okay";
> + flash@0 {
> + compatible = "jedec,spi-nor";
You need a specific type of the qpsi memory here.
> + reg = <0>;
> + spi-max-frequency = <100000000>;
> + m25p,fast-read;
> + cdns,read-delay = <2>;
> + cdns,tshsl-ns = <50>;
> + cdns,tsd2d-ns = <50>;
> + cdns,tchsh-ns = <4>;
> + cdns,tslch-ns = <4>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + qspi_boot: partition@0 {
> + label = "u-boot";
> + reg = <0x0 0x00600000>;
> + };
> +
> + root: partition@...0000 {
> + label = "root";
> + reg = <0x00600000 0x03a00000>;
> + };
> + };
> + };
> +};
> +
> +&smmu {
> + status = "okay";
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
No USB?
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