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Message-ID: <t45yq2cqj2t7lv4ifnvv556ewznjtzhdvvmofzgb5kcsarydqe@hxtonnejw6t7>
Date: Wed, 12 Nov 2025 22:08:57 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: manivannan.sadhasivam@....qualcomm.com
Cc: Rob Herring <robh@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>,
Nathan Chancellor <nathan@...nel.org>,
Nicolas Schier <nicolas.schier@...ux.dev>,
Hans de Goede <hansg@...nel.org>,
Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
Mark Pearson <mpearson-lenovo@...ebb.ca>,
"Derek J. Clark" <derekjohn.clark@...il.com>,
Manivannan Sadhasivam <mani@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Marcel Holtmann <marcel@...tmann.org>,
Luiz Augusto von Dentz <luiz.dentz@...il.com>,
Bartosz Golaszewski <brgl@...ev.pl>, linux-serial@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-kbuild@...r.kernel.org,
platform-driver-x86@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-bluetooth@...r.kernel.org, linux-pm@...r.kernel.org,
Stephan Gerhold <stephan.gerhold@...aro.org>
Subject: Re: [PATCH 7/9] dt-bindings: connector: Add PCIe M.2 Mechanical Key
E connector
On Wed, Nov 12, 2025 at 08:15:19PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
>
> Add the devicetree binding for PCIe M.2 Mechanical Key E connector defined
> in the PCI Express M.2 Specification, r4.0, sec 5.1.2. This connector
> provides interfaces like PCIe or SDIO to attach the WiFi devices to the
> host machine, USB or UART+PCM interfaces to attach the Bluetooth (BT)
> devices along with additional interfaces like I2C for NFC solution. At any
> point of time, the connector can only support either PCIe or SDIO as the
> WiFi interface and USB or UART as the BT interface.
>
> The connector provides a primary power supply of 3.3v, along with an
> optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at
> 1.8v sideband signaling.
>
> The connector also supplies optional signals in the form of GPIOs for fine
> grained power management.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
> ---
> .../bindings/connector/pcie-m2-e-connector.yaml | 154 +++++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 155 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..91cb56b1a75b7e3de3b9fe9a7537089f96875746
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
> @@ -0,0 +1,154 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: PCIe M.2 Mechanical Key E Connector
> +
> +maintainers:
> + - Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
> +
> +description:
> + A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E
> + connector. Mechanical Key E connectors are used to connect Wireless
> + Connectivity devices including combinations of Wi-Fi, BT, NFC to the host
> + machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C.
> +
> +properties:
> + compatible:
> + const: pcie-m2-e-connector
> +
> + vpcie3v3-supply:
> + description: A phandle to the regulator for 3.3v supply.
> +
> + vpcie1v8-supply:
> + description: A phandle to the regulator for VIO 1.8v supply.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + description: OF graph bindings modeling the interfaces exposed on the
> + connector. Since a single connector can have multiple interfaces, every
> + interface has an assigned OF graph port number as described below.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: PCIe/SDIO interface
The same comment as for the M-key bindings: please describe endpoints.
> + led1-gpios:
> + description: GPIO controlled connection to LED_1# signal. This signal is
> + used by the M.2 card to indicate the card status via the system mounted
> + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more
> + details.
How are we supposed to handle these LEDs? I have been assuming that
these pins should go striaght to the LED driver.
> + maxItems: 1
> +
> + led2-gpios:
> + description: GPIO controlled connection to LED_2# signal. This signal is
> + used by the M.2 card to indicate the card status via the system mounted
> + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more
> + details.
> + maxItems: 1
> +
> + viocfg-gpios:
> + description: GPIO controlled connection to IO voltage configuration
> + (VIO_CFG) signal. This signal is used by the M.2 card to indicate to the
> + host system that the card supports an independent IO voltage domain for
> + the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec
> + 3.1.15.1 for more details.
> + maxItems: 1
This more looks like viocfg-supply. Looking at this one and several
other pins, it's more like a GPIO controller, providing those pins for
the system, rather than a GPIO consumer.
> +
> + uim_power_src-gpios:
> + description: GPIO controlled connection to UIM_POWER_SRC signal. This signal
> + is used when the NFC solution is implemented and receives the power output
> + from WWAN_UIM_PWR signal of the another WWAN M.2 card. Refer, PCI Express
> + M.2 Specification r4.0, sec 3.1.11.1 for more details.
> + maxItems: 1
> +
> + uim_power_snk-gpios:
> + description: GPIO controlled connection to UIM_POWER_SNK signal. This signal
> + is used when the NFC solution is implemented and supplies power to the
> + Universal Integrated Circuit Card (UICC). Refer, PCI Express M.2
> + Specification r4.0, sec 3.1.11.2 for more details.
> + maxItems: 1
> +
> + uim_swp-gpios:
> + description: GPIO controlled connection to UIM_SWP signal. This signal is
> + used when the NFC solution is implemented and implements the Single Wire
> + Protocol (SWP) interface to the UICC. Refer, PCI Express M.2 Specification
> + r4.0, sec 3.1.11.3 for more details.
> + maxItems: 1
> +
> +required:
> + - compatible
> + - vpcie3v3-supply
> +
> +additionalProperties: false
> +
> +examples:
> + # PCI M.2 Key E connector for WLAN/BT with PCIe/UART interfaces
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> +
> + connector {
> + compatible = "pcie-m2-e-connector";
> + vpcie3v3-supply = <&vreg_wcn_3p3>;
> + vpcie1v8-supply = <&vreg_l15b_1p8>;
> + w_disable1-gpios = <&tlmm 117 GPIO_ACTIVE_LOW>;
> + w_disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + endpoint {
> + remote-endpoint = <&pcie4_port0_ep>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> +
> + endpoint {
> + remote-endpoint = <&uart14_ep>;
> + };
> + };
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9b3f689d1f50c62afa3772a0c6802f99a98ac2de..f707f29d0a37f344d8dd061b7e49dbb807933c9f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20478,6 +20478,7 @@ PCIE M.2 POWER SEQUENCING
> M: Manivannan Sadhasivam <mani@...nel.org>
> L: linux-pci@...r.kernel.org
> S: Maintained
> +F: Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
> F: Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml
> F: drivers/power/sequencing/pwrseq-pcie-m2.c
>
>
> --
> 2.48.1
>
>
--
With best wishes
Dmitry
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