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Message-ID: <0d8e3a626b037dd348378e5ebca8005c1e715871.camel@icenowy.me>
Date: Wed, 12 Nov 2025 14:34:39 +0800
From: Icenowy Zheng <uwu@...nowy.me>
To: Conor Dooley <conor@...nel.org>, Michal Wilczynski
<m.wilczynski@...sung.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Emil Renner Berthing <kernel@...il.dk>, Hal Feng
<hal.feng@...rfivetech.com>, Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Xingyu
Wu <xingyu.wu@...rfivetech.com>, Vinod Koul <vkoul@...nel.org>, Kishon
Vijay Abraham I <kishon@...nel.org>, Andrzej Hajda
<andrzej.hajda@...el.com>, Neil Armstrong <neil.armstrong@...aro.org>,
Robert Foss <rfoss@...nel.org>, Laurent Pinchart
<Laurent.pinchart@...asonboard.com>, Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>, David Airlie
<airlied@...il.com>, Simona Vetter <simona@...ll.ch>, Maarten Lankhorst
<maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, Lee Jones <lee@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>, Paul Walmsley
<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou
<aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>, Marek Szyprowski
<m.szyprowski@...sung.com>, Maud Spierings <maudspierings@...ontroll.com>,
Andy Yan <andyshrk@....com>, Heiko Stuebner <heiko@...ech.de>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, linux-phy@...ts.infradead.org,
dri-devel@...ts.freedesktop.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH RFC 01/13] dt-bindings: soc: starfive: Add
vout-subsystem IP block
在 2025-11-11星期二的 18:36 +0000，Conor Dooley写道：
> On Tue, Nov 11, 2025 at 06:18:16PM +0000, Conor Dooley wrote:
> > On Sat, Nov 08, 2025 at 02:04:35AM +0100, Michal Wilczynski wrote:
> > > Add the dt-binding documentation for the StarFive JH7110 Video
> > > Output
> > > (VOUT) subsystem.
> > >
> > > This node acts as a parent for all devices within the VOUT power
> > > domain,
> > > including the DC8200 display controller, the VOUTCRG clock
> > > generator,
> > > and the HDMI MFD block. Its driver is responsible for managing
> > > the
> > > shared power domain and top-level bus clocks for these children.
> > >
> > > It is a bit similar to the display subsystem qcom,sdm845-mdss DT
> > > node.
> > >
> > > Signed-off-by: Michal Wilczynski <m.wilczynski@...sung.com>
> > > ---
> > > .../starfive/starfive,jh7110-vout-subsystem.yaml | 156
> > > +++++++++++++++++++++
> > > MAINTAINERS | 5 +
> > > 2 files changed, 161 insertions(+)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-
> > > vout-subsystem.yaml
> > > b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-
> > > vout-subsystem.yaml
> > > new file mode 100644
> > > index
> > > 0000000000000000000000000000000000000000..4ad9423ea139a537b4cfea2
> > > 6b0ed4ed263aa14a1
> > > --- /dev/null
> > > +++
> > > b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-
> > > vout-subsystem.yaml
> > > @@ -0,0 +1,156 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id:
> > > http://devicetree.org/schemas/soc/starfive/starfive,jh7110-vout-subsystem.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: StarFive JH7110 VOUT (Video Output) Subsystem
> > > +
> > > +maintainers:
> > > + - Michal Wilczynski <m.wilczynski@...sung.com>
> > > +
> > > +description:
> > > + The JH7110 video output subsystem is an IP block that contains
> > > + the display controller (DC8200), HDMI controller/PHY, and VOUT
> > > + clock generator (VOUTCRG).
> > > +
> > > +properties:
> > > + compatible:
> > > + const: starfive,jh7110-vout-subsystem
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + power-domains:
> > > + maxItems: 1
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > +
> > > + resets:
> > > + maxItems: 1
> > > +
> > > + ranges: true
> > > +
> > > + '#address-cells':
> > > + const: 2
> > > +
> > > + '#size-cells':
> > > + const: 2
> > > +
> > > +patternProperties:
> > > + "^display@[0-9a-f]+$":
> >
> > Personally I'd like to see these being regular properties, since
> > there's
> > exactly one possible setup for this.
> >
> > > + type: object
> > > + description: Verisilicon DC8200 Display Controller node.
> >
> > Can you add the relevant references here instead of allowing any
> > object?
>
> I don't think that if you did, this would pass the binding checks,
> because there's no "verisilicon,dc" binding. I think I saw one in
> progress, but without the soc-specific compatible that I am going to
> require here - if for no reason other than making sure that the
> clocks
> etc are provided correctly for this device.
Well I didn't specify any soc-specific compatible because that IP has
its own identification registers.
>
> >
> > Cheers,
> > Conor.
> >
> > > +
> > > + "^hdmi@[0-9a-f]+$":
> > > + type: object
> > > + description: StarFive HDMI MFD (PHY + Controller) node.
> > > +
> > > + "^clock-controller@[0-9a-f]+$":
> > > + type: object
> > > + description: StarFive VOUT Clock Generator (VOUTCRG) node.
> > > +
> > > + "^syscon@[0-9a-f]+$":
> > > + type: object
> > > + description: StarFive VOUT Syscon node.
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - power-domains
> > > + - clocks
> > > + - resets
> > > + - ranges
> > > + - '#address-cells'
> > > + - '#size-cells'
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/clock/starfive,jh7110-crg.h>
> > > + #include <dt-bindings/power/starfive,jh7110-pmu.h>
> > > + #include <dt-bindings/reset/starfive,jh7110-crg.h>
> > > +
> > > + soc {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > +
> > > + vout_subsystem: display-subsystem@...00000 {
> > > + compatible = "starfive,jh7110-vout-subsystem";
> > > + reg = <0x0 0x29400000 0x0 0x200000>;
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + ranges;
> > > +
> > > + power-domains = <&pwrc JH7110_PD_VOUT>;
> > > + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>;
> > > + resets = <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>;
> > > +
> > > + dc8200: display@...00000 {
> > > + compatible = "verisilicon,dc";
> > > + reg = <0x0 0x29400000 0x0 0x2800>;
> > > + interrupts = <95>;
> > > + clocks = <&voutcrg JH7110_VOUTCLK_DC8200_CORE>,
> > > + <&voutcrg JH7110_VOUTCLK_DC8200_AXI>,
> > > + <&voutcrg JH7110_VOUTCLK_DC8200_AHB>,
> > > + <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>,
> > > + <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>;
> > > + clock-names = "core", "axi", "ahb", "pix0",
> > > "pix1";
> > > + resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>,
> > > + <&voutcrg JH7110_VOUTRST_DC8200_AHB>,
> > > + <&voutcrg JH7110_VOUTRST_DC8200_CORE>;
> > > + reset-names = "axi", "ahb", "core";
> > > + };
> > > +
> > > + hdmi_mfd: hdmi@...90000 {
> > > + compatible = "starfive,jh7110-hdmi-mfd";
> > > + reg = <0x0 0x29590000 0x0 0x4000>;
> > > + interrupts = <99>;
> > > +
> > > + hdmi_phy: phy {
> > > + compatible = "starfive,jh7110-inno-hdmi-
> > > phy";
> > > + clocks = <&xin24m>;
> > > + clock-names = "refoclk";
> > > + #clock-cells = <0>;
> > > + clock-output-names = "hdmi_pclk";
> > > + #phy-cells = <0>;
> > > + };
> > > +
> > > + hdmi_controller: controller {
> > > + compatible = "starfive,jh7110-inno-hdmi-
> > > controller";
> > > + interrupts = <99>;
> > > + clocks = <&voutcrg
> > > JH7110_VOUTCLK_HDMI_TX_SYS>,
> > > + <&voutcrg
> > > JH7110_VOUTCLK_HDMI_TX_MCLK>,
> > > + <&voutcrg
> > > JH7110_VOUTCLK_HDMI_TX_BCLK>,
> > > + <&hdmi_phy>;
> > > + clock-names = "sys", "mclk", "bclk", "pclk";
> > > + resets = <&voutcrg
> > > JH7110_VOUTRST_HDMI_TX_HDMI>;
> > > + reset-names = "hdmi_tx";
> > > + phys = <&hdmi_phy>;
> > > + phy-names = "hdmi-phy";
> > > + };
> > > + };
> > > +
> > > + voutcrg: clock-controller@...c0000 {
> > > + compatible = "starfive,jh7110-voutcrg";
> > > + reg = <0x0 0x295c0000 0x0 0x10000>;
> > > + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
> > > + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
> > > + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
> > > + <&syscrg
> > > JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
> > > + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
> > > + <&hdmi_phy>;
> > > + clock-names = "vout_src", "vout_top_ahb",
> > > + "vout_top_axi",
> > > "vout_top_hdmitx0_mclk",
> > > + "i2stx0_bclk", "hdmitx0_pixelclk";
> > > + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
> > > + reset-names = "vout_top";
> > > + #clock-cells = <1>;
> > > + #reset-cells = <1>;
> > > + };
> > > + };
> > > + };
> > > +
> > > +...
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index
> > > 348caaaa929a519bc0ec5c0c7b587468ef7532d5..99434e54dc39494153677a6
> > > ca359d70f2ba2ddb3 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -24044,6 +24044,11 @@ S: Maintained
> > > F: Documentation/devicetree/bindings/net/starfive,jh7110-
> > > dwmac.yaml
> > > F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
> > >
> > > +STARFIVE JH7110 DISPLAY SUBSYSTEM
> > > +M: Michal Wilczynski <m.wilczynski@...sung.com>
> > > +S: Maintained
> > > +F: Documentation/devicetree/bindings/soc/starfive/starfive,j
> > > h7110-vout-subsystem.yaml
> > > +
> > > STARFIVE JH7110 DPHY RX DRIVER
> > > M: Jack Zhu <jack.zhu@...rfivetech.com>
> > > M: Changhuang Liang <changhuang.liang@...rfivetech.com>
> > >
> > > --
> > > 2.34.1
> > >
>
>
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