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Message-ID: <1a8dcc37-68a3-463f-874e-8bb808047d2d@linux.intel.com>
Date: Wed, 12 Nov 2025 08:16:58 +0800
From: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo
 <acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
 Ian Rogers <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Andi Kleen <ak@...ux.intel.com>, Eranian Stephane <eranian@...gle.com>,
 linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
 Dapeng Mi <dapeng1.mi@...el.com>, Zide Chen <zide.chen@...el.com>,
 Falcon Thomas <thomas.falcon@...el.com>, Xudong Hao <xudong.hao@...el.com>
Subject: Re: [Patch v9 10/12] perf/x86/intel: Update dyn_constranit base on
 PEBS event precise level


On 11/11/2025 7:37 PM, Peter Zijlstra wrote:
> On Tue, Nov 11, 2025 at 01:41:05PM +0800, Mi, Dapeng wrote:
>
>> I tested the queue/perf/core code with a slight code refine on SPR/CWF/PTL.
>> In summary, all things look good. The constraints validation passes on all
>> these 3 platforms, no overlapped constraints are reported. Besides, perf
>> counting/sampling (both legacy PEBS and arch-PEBS) works well, no issue is
>> found.
> Excellent, I pushed out to tip/perf/core.
>
>> I did a slight change for the intel_pmu_check_dyn_constr() helper. It
>> should be good enough to only validate the GP counters for the PEBS counter
>> and PDIST constraint check. Beside the code style is refined
>> opportunistically. Thanks.
> If you could send that as a proper patch -- the thing was horribly
> whitespace mangled.

Sure. Would send the patch soon.



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