linux-kernel - Re: [PATCH v3 4/5] mtd: spi-nor: micron-st: add mt35xu01gbba support

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Message-ID: <76970e66-7191-4e33-9def-4f28c414a125@linaro.org>
Date: Wed, 12 Nov 2025 11:07:47 +0200
From: Tudor Ambarus <tudor.ambarus@...aro.org>
To: Haibo Chen <haibo.chen@....com>, Pratyush Yadav <pratyush@...nel.org>,
 Michael Walle <mwalle@...nel.org>, Miquel Raynal
 <miquel.raynal@...tlin.com>, Richard Weinberger <richard@....at>,
 Vignesh Raghavendra <vigneshr@...com>
Cc: linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org,
 imx@...ts.linux.dev
Subject: Re: [PATCH v3 4/5] mtd: spi-nor: micron-st: add mt35xu01gbba support



On 11/12/25 8:48 AM, Haibo Chen wrote:
> mt35xu01gbba is similar with mt35xu512aba, but with two dies.
> mt35xu01gbba has SFDP and support 8D-8D-8D mode, but SFDP
> lack SNOR_F_IO_MODE_EN_VOLATILE, so add this fixup flags here.
> Besides, mt35xu01gbba do not support chip erase, but support
> die erase, so add that in late_init().
> 
> Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf
> Signed-off-by: Haibo Chen <haibo.chen@....com>
> 
> ---
> 1) This mt35xu01gbba is populated on the imx95-19x19-evk board, was
>    tested at 200MHz using nxp,imx95-fspi SPI controller.
> 2) root@...95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/jedec_id
>    2c5b1b
>    root@...95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/manufacturer
>    micron
>    root@...95evk:~# hexdump -Cv /sys/bus/spi/devices/spi1.0/spi-nor/sfdp
>    00000000  53 46 44 50 0a 01 03 ff  00 08 01 17 30 00 00 ff  |SFDP........0...|
>    00000010  84 00 01 02 90 00 00 ff  05 01 01 06 a0 00 00 ff  |................|
>    00000020  0a 00 01 08 b0 00 00 ff  ff ff ff ff ff ff ff ff  |................|
>    00000030  e5 20 8a ff ff ff ff 3f  00 00 00 00 00 00 00 00  |. .....?........|
>    00000040  ee ff ff ff ff ff 00 00  ff ff 00 00 0c 20 11 d8  |............. ..|
>    00000050  0f 52 00 00 39 61 99 00  87 8e 03 d3 ac a1 27 3d  |.R..9a........'=|
>    00000060  7a 75 7a 75 fb bd d5 5c  00 00 70 ff 81 50 f8 a1  |zuzu...\..p..P..|
>    00000070  2f cb 27 8b 00 00 04 01  00 06 01 00 ff ff ff 8e  |/.'.............|
>    00000080  00 00 00 00 00 00 00 00  00 00 00 00 ff ff ff ff  |................|
>    00000090  43 0e ff ff 21 dc 5c ff  ff ff ff ff ff ff ff ff  |C...!.\.........|
>    000000a0  00 0b 80 9e b1 81 b5 85  00 f0 ff 9f 00 0a 00 00  |................|
>    000000b0  00 0a 1a 88 10 00 00 00  ff ff ff ff ff ff ff ff  |................|
>    000000c0  00 00 06 01 00 00 00 00  14 01 81 03 00 00 00 00  |................|
>    000000d0

SFDP above

>  		/* MT35XU512ABA */
> @@ -193,6 +198,13 @@ static const struct flash_info micron_nor_parts[] = {
>  		.mfr_flags = USE_FSR,
>  		.fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
>  		.fixups = &mt35xu512aba_fixups,
> +	}, {
> +		/* MT35XU01GBBA */
> +		.id = SNOR_ID(0x2c, 0x5b, 0x1b),
> +		.sector_size = SZ_128K,

you can drop sector_size, can't you?

> +		.mfr_flags = USE_FSR,
> +		.fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
> +		.fixups = &mt35xu01gbba_fixups,
>  	}, {
>  		.id = SNOR_ID(0x2c, 0x5b, 0x1c),
>  		.name = "mt35xu02g",
>