linux-kernel - Re: [PATCH v6 1/2] PCI: Configure Root Port MPS during host probing

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Message-ID: <6bd16478-4bf9-436a-b862-02d1ebac3d29@cixtech.com>
Date: Wed, 12 Nov 2025 19:04:10 +0800
From: Hans Zhang <hans.zhang@...tech.com>
To: Shawn Lin <shawn.lin@...k-chips.com>, Hans Zhang <18255117159@....com>,
 lpieralisi@...nel.org, kwilczynski@...nel.org, bhelgaas@...gle.com,
 helgaas@...nel.org, heiko@...ech.de, mani@...nel.org, yue.wang@...ogic.com
Cc: pali@...nel.org, neil.armstrong@...aro.org, robh@...nel.org,
 jingoohan1@...il.com, khilman@...libre.com, jbrunet@...libre.com,
 martin.blumenstingl@...glemail.com, cassel@...nel.org,
 linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-amlogic@...ts.infradead.org,
 linux-rockchip@...ts.infradead.org
Subject: Re: [PATCH v6 1/2] PCI: Configure Root Port MPS during host probing



On 11/12/2025 4:31 PM, Shawn Lin wrote:
> EXTERNAL EMAIL
> 
> 在 2025/11/05 星期三 0:51, Hans Zhang 写道:
>> Current PCIe initialization logic may leave Root Ports (root bridges)
>> operating with non-optimal Maximum Payload Size (MPS) settings. Existing
>> code in pci_configure_mps() returns early for devices without an upstream
>> bridge (!bridge) which includes Root Ports, so their MPS values remain
>> at firmware/hardware defaults. This fails to utilize the controller's 
>> full
>> capabilities, leading to suboptimal data transfer efficiency across the
>> PCIe hierarchy.
>>
>> With this patch, during the host controller probing phase:
>> - When PCIe bus tuning is enabled (not PCIE_BUS_TUNE_OFF), and
>> - The device is a Root Port without an upstream bridge (!bridge),
>> The Root Port's MPS is set to its hardware-supported maximum value
>> (128 << dev->pcie_mpss).
>>
>> Note that this initial maximum MPS setting may be reduced later, during
>> downstream device enumeration, if any downstream device does not suppor
>> the Root Port's maximum MPS.
>>
>> This change ensures Root Ports are properly initialized before downstream
>> devices negotiate MPS, while maintaining backward compatibility via the
>> PCIE_BUS_TUNE_OFF check.
>>
> 
> Tested-by: Shawn Lin <shawn.lin@...k-chips.com>

Hi Shawn,

Thank you for your test.

Best regards,
Hans

> 
>> Suggested-by: Niklas Cassel <cassel@...nel.org>
>> Suggested-by: Manivannan Sadhasivam <mani@...nel.org>
>> Signed-off-by: Hans Zhang <18255117159@....com>
>> ---
>>   drivers/pci/probe.c | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
>> index 0ce98e18b5a8..2459def3af9b 100644
>> --- a/drivers/pci/probe.c
>> +++ b/drivers/pci/probe.c
>> @@ -2196,6 +2196,18 @@ static void pci_configure_mps(struct pci_dev *dev)
>>               return;
>>       }
>>
>> +     /*
>> +      * Unless MPS strategy is PCIE_BUS_TUNE_OFF (don't touch MPS at 
>> all),
>> +      * start off by setting Root Ports' MPS to MPSS. This only 
>> applies to
>> +      * Root Ports without an upstream bridge (root bridges), as 
>> other Root
>> +      * Ports will have downstream bridges. Depending on the MPS 
>> strategy
>> +      * and MPSS of downstream devices, the Root Port's MPS may be
>> +      * overridden later.
>> +      */
>> +     if (!bridge && pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT &&
>> +         pcie_bus_config != PCIE_BUS_TUNE_OFF)
>> +             pcie_set_mps(dev, 128 << dev->pcie_mpss);
>> +
>>       if (!bridge || !pci_is_pcie(bridge))
>>               return;
>>
> 
>