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Message-ID: <5a084954898.59053dc9@mail.gmx.com>
Date: Wed, 12 Nov 2025 13:15:44 +0200 (EET)
From: Roland <rol7and@....com>
To: Bjorn Helgaas <helgaas@...nel.org>
CC: linux-pci@...r.kernel.org,
Christian Zigotzky <chzigotzky@...osoft.de>,
Manivannan Sadhasivam <mani@...nel.org>,
mad skateman <madskateman@...il.com>,
R . T . Dickinson <rtd2@...a.co.nz>,
Darren Stevens <darren@...vens-zone.net>,
John Paul Adrian Glaubitz <glaubitz@...sik.fu-berlin.de>,
Lukas Wunner <lukas@...ner.de>,
luigi burdo <intermediadc@...mail.com>,
Al <al@...azap.net>,
Hongxing Zhu <hongxing.zhu@....com>,
hypexed@...oo.com.au,
linuxppc-dev@...ts.ozlabs.org,
debian-powerpc@...ts.debian.org,
linux-kernel@...r.kernel.org,
Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: PCI/ASPM: Allow quirks to avoid L0s and L1
Hello all!
I started to get to my email these discussions about Linux a few days ago. I have not subscribed any mailing list, or given anyone permission to include my name on such list!
So, if there is a moderator on this list, could you PLEASE remove immediately my email (rol7and@....com) from the recipients/cc list? Thank you!
If there is no moderator, could the participants then please take care to remove my email from their messages? Thank you!
Regards,
Roland
> On Mon, Nov 10, 2025 at 04:22:24PM -0600, Bjorn Helgaas wrote:
>> From: Bjorn Helgaas <bhelgaas@...gle.com>
>>
>> We enabled ASPM too aggressively in v6.18-rc1. f3ac2ff14834 ("PCI/ASPM:
>> Enable all ClockPM and ASPM states for devicetree platforms") enabled
>> ASPM L0s, L1, and (if advertised) L1 PM Substates.
>>
>> df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for devicetree
>> platforms") (v6.18-rc3) backed off and omitted Clock PM and L1 Substates
>> because we don't have good infrastructure to discover CLKREQ# support,
>> and L1 Substates may require device-specific configuration.
>>
>> L0s and L1 are generically discoverable and should not require
>> device-specific support, but some devices advertise them even though
>> they don't work correctly. This series is a way to add quirks avoid L0s
>> and L1 in this case.
>>
>>
>> Bjorn Helgaas (4):
>> PCI/ASPM: Cache L0s/L1 Supported so advertised link states can be
>> overridden
>> PCI/ASPM: Add pcie_aspm_remove_cap() to override advertised link
>> states
>> PCI/ASPM: Convert quirks to override advertised link states
>> PCI/ASPM: Avoid L0s and L1 on Freescale Root Ports
>>
>> drivers/pci/pci.h | 2 ++
>> drivers/pci/pcie/aspm.c | 25 +++++++++++++++++--------
>> drivers/pci/probe.c | 7 +++++++
>> drivers/pci/quirks.c | 38 +++++++++++++++++++-------------------
>> include/linux/pci.h | 2 ++
>> 5 files changed, 47 insertions(+), 27 deletions(-)
>
> Applied to pci/for-linus, hoping for v6.18. Thanks Shawn and Lukas
> for testing and reviewing. Any other comments and testing would be
> very welcome.
>
> I think we'll need to add a similar quirk for Christian's X1000
> (https://lore.kernel.org/r/a41d2ca1-fcd9-c416-b111-a958e92e94bf@xenosoft.de),
> but I don't know the device ID for it yet.
>
>> --
>>
>> v1:
>> https://lore.kernel.org/r/20251106183643.1963801-1-helgaas@kernel.org
>
>> Changes between v1 and v2:
>> - Cache just the two bits for L0s and L1 support, not the entire Link
>> Capabilities (Lukas)
>> - Add pcie_aspm_remove_cap() to override the ASPM Support bits in Link
>> Capabilities (Lukas)
>> - Convert existing quirks to use pcie_aspm_remove_cap() instead of
>> pci_disable_link_state(), and from FINAL to HEADER (Mani)
Regards
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