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Message-ID: <20251112-upstream_uboot_properties-v1-2-0b19133710e3@foss.st.com>
Date: Wed, 12 Nov 2025 11:46:44 +0100
From: Patrice Chotard <patrice.chotard@...s.st.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin
<mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Patrick Delaunay <patrick.delaunay@...s.st.com>
CC: <devicetree@...r.kernel.org>, <linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
Patrice Chotard <patrice.chotard@...s.st.com>
Subject: [PATCH 2/6] ARM: dts: stm32: Add boot phase tags for
STMicroelectronics f7 boards
The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.
To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.
Signed-off-by: Patrice Chotard <patrice.chotard@...s.st.com>
---
arch/arm/boot/dts/st/stm32746g-eval.dts | 10 ++++++++++
arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi | 11 +++++++++++
arch/arm/boot/dts/st/stm32f746-disco.dts | 12 ++++++++++++
arch/arm/boot/dts/st/stm32f746.dtsi | 5 +++++
arch/arm/boot/dts/st/stm32f769-disco.dts | 12 ++++++++++++
5 files changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts
index e9ac37b6eca0..26c5796a81fb 100644
--- a/arch/arm/boot/dts/st/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/st/stm32746g-eval.dts
@@ -213,6 +213,16 @@ &usart1 {
status = "okay";
};
+&usart1_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
&usbotg_hs {
dr_mode = "otg";
phys = <&usbotg_hs_phy>;
diff --git a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
index 97fc3fb5a9ca..6b01c3c84272 100644
--- a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
@@ -24,6 +24,7 @@ gpioa: gpio@...20000 {
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
+ bootph-all;
};
gpiob: gpio@...20400 {
@@ -34,6 +35,7 @@ gpiob: gpio@...20400 {
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
+ bootph-all;
};
gpioc: gpio@...20800 {
@@ -44,6 +46,7 @@ gpioc: gpio@...20800 {
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
+ bootph-all;
};
gpiod: gpio@...20c00 {
@@ -54,6 +57,7 @@ gpiod: gpio@...20c00 {
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
+ bootph-all;
};
gpioe: gpio@...21000 {
@@ -64,6 +68,7 @@ gpioe: gpio@...21000 {
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
+ bootph-all;
};
gpiof: gpio@...21400 {
@@ -74,6 +79,7 @@ gpiof: gpio@...21400 {
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
+ bootph-all;
};
gpiog: gpio@...21800 {
@@ -84,6 +90,7 @@ gpiog: gpio@...21800 {
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
+ bootph-all;
};
gpioh: gpio@...21c00 {
@@ -94,6 +101,7 @@ gpioh: gpio@...21c00 {
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
+ bootph-all;
};
gpioi: gpio@...22000 {
@@ -104,6 +112,7 @@ gpioi: gpio@...22000 {
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
+ bootph-all;
};
gpioj: gpio@...22400 {
@@ -114,6 +123,7 @@ gpioj: gpio@...22400 {
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
+ bootph-all;
};
gpiok: gpio@...22800 {
@@ -124,6 +134,7 @@ gpiok: gpio@...22800 {
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
+ bootph-all;
};
cec_pins_a: cec-0 {
diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts
index b57dbdce2f40..9545b14d77c3 100644
--- a/arch/arm/boot/dts/st/stm32f746-disco.dts
+++ b/arch/arm/boot/dts/st/stm32f746-disco.dts
@@ -169,6 +169,7 @@ touchscreen@38 {
<dc {
pinctrl-0 = <<dc_pins_a>;
pinctrl-names = "default";
+ bootph-all;
status = "okay";
port {
@@ -207,6 +208,17 @@ &usart1 {
status = "okay";
};
+
+&usart1_pins_b {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
&usbotg_fs {
dr_mode = "host";
pinctrl-0 = <&usbotg_fs_pins_a>;
diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi
index 208f8c6dfc9d..b0f012de759c 100644
--- a/arch/arm/boot/dts/st/stm32f746.dtsi
+++ b/arch/arm/boot/dts/st/stm32f746.dtsi
@@ -54,6 +54,7 @@ clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
+ bootph-all;
};
clk-lse {
@@ -76,6 +77,7 @@ clk_i2s_ckin: clk-i2s-ckin {
};
soc {
+ bootph-all;
timers2: timers@...00000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -149,6 +151,7 @@ timers5: timers@...00c00 {
reg = <0x40000C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
clock-names = "int";
+ bootph-all;
status = "disabled";
pwm {
@@ -645,6 +648,7 @@ ltdc: display-controller@...16800 {
pwrcfg: power-config@...07000 {
compatible = "st,stm32-power-config", "syscon";
reg = <0x40007000 0x400>;
+ bootph-all;
};
crc: crc@...23000 {
@@ -663,6 +667,7 @@ rcc: rcc@...23800 {
st,syscfg = <&pwrcfg>;
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
assigned-clock-rates = <1000000>;
+ bootph-all;
};
dma1: dma-controller@...26000 {
diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts
index 535cfdc4681c..539517c7991e 100644
--- a/arch/arm/boot/dts/st/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/st/stm32f769-disco.dts
@@ -133,6 +133,7 @@ &clk_hse {
&dsi {
#address-cells = <1>;
#size-cells = <0>;
+ bootph-all;
status = "okay";
ports {
@@ -178,6 +179,7 @@ &i2c1 {
};
<dc {
+ bootph-all;
status = "okay";
port {
@@ -221,6 +223,16 @@ &usart1 {
status = "okay";
};
+&usart1_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
&usbotg_hs {
dr_mode = "otg";
phys = <&usbotg_hs_phy>;
--
2.43.0
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