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Message-ID:
<TY3PR01MB1134641A7641EF0C0F0086C9E86CDA@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Thu, 13 Nov 2025 14:10:49 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: geert <geert@...ux-m68k.org>, biju.das.au <biju.das.au@...il.com>
CC: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby
<jirislaby@...nel.org>, wsa+renesas <wsa+renesas@...g-engineering.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>, Claudiu
Beznea <claudiu.beznea.uj@...renesas.com>, Nam Cao <namcao@...utronix.de>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-serial@...r.kernel.org" <linux-serial@...r.kernel.org>,
"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
"stable@...nel.org" <stable@...nel.org>
Subject: RE: [PATCH v2 2/2] serial: sh-sci: Fix deadlock during RSCI FIFO
overrun error
Hi Geert,
Thanks for the feedback.
> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: 06 November 2025 16:51
> Subject: Re: [PATCH v2 2/2] serial: sh-sci: Fix deadlock during RSCI FIFO overrun error
>
> Hi Biju,
>
> On Wed, 29 Oct 2025 at 09:21, Biju <biju.das.au@...il.com> wrote:
> > From: Biju Das <biju.das.jz@...renesas.com>
> >
> > On RSCI IP, a deadlock occurs during a FIFO overrun error, as it uses
> > a different register to clear the FIFO overrun error status.
> >
> > Cc: stable@...nel.org
> > Fixes: 0666e3fe95ab ("serial: sh-sci: Add support for RZ/T2H SCI")
> > Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/tty/serial/rsci.c
> > +++ b/drivers/tty/serial/rsci.c
> > @@ -414,6 +414,7 @@ static const struct sci_port_params_bits rsci_port_param_bits = {
> > .rxtx_enable = CCR0_RE | CCR0_TE,
> > .te_clear = CCR0_TE | CCR0_TEIE,
> > .poll_sent_bits = CSR_TDRE | CSR_TEND,
> > + .overrun_clr = CFCLR_ORERC,
> > };
> >
> > static const struct sci_port_params rsci_port_params = { diff --git
> > a/drivers/tty/serial/sh-sci-common.h
> > b/drivers/tty/serial/sh-sci-common.h
> > index e3c028df14f1..bcdb41ddc15d 100644
> > --- a/drivers/tty/serial/sh-sci-common.h
> > +++ b/drivers/tty/serial/sh-sci-common.h
> > @@ -51,6 +51,7 @@ struct sci_port_params_bits {
> > unsigned int rxtx_enable;
> > unsigned int te_clear;
> > unsigned int poll_sent_bits;
> > + unsigned int overrun_clr;
>
> I don't really see a need to add this field, as there are two alternatives...
OK.
>
> > };
> >
> > struct sci_common_regs {
> > diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> > index 62bb62b82cbe..b33894d0273b 100644
> > --- a/drivers/tty/serial/sh-sci.c
> > +++ b/drivers/tty/serial/sh-sci.c
> > @@ -1024,8 +1024,12 @@ static int sci_handle_fifo_overrun(struct
> > uart_port *port)
> >
> > status = s->ops->read_reg(port, s->params->overrun_reg);
> > if (status & s->params->overrun_mask) {
> > - status &= ~s->params->overrun_mask;
> > - s->ops->write_reg(port, s->params->overrun_reg, status);
> > + if (s->type == SCI_PORT_RSCI) {
> > + s->ops->clear_SCxSR(port,
> > + s->params->param_bits->overrun_clr);
>
> 1. You can just use CFCLR_ORERC directly here,
This means, I need to move the macro CFCLR_ORERC for rsci.c->sh-sci.c.
2. All of the CFCLR_*C clearing bits match the
> corresponding CSR_*
> status bits, so you could do without the former, and thus use
> params->overrun_mask here, too.
OK, I will put a comment like above and use params->overrun_mask here.
>
> > + } else {
> > + status &= ~s->params->overrun_mask;
> > + s->ops->write_reg(port, s->params->overrun_reg, status);
> > + }
> >
> > port->icount.overrun++;
> >
>
> BTW, how is this related to "[PATCH] tty: serial: sh-sci: fix RSCI FIFO overrun handling" [1], which
> is already applied (and which I still don't fully understand the big picture behind. I'll reply
> there)?
For me it is a surprise, for deadlock did not happen in that instance, as the overrun error path
never clear the interrupt.
Cheers,
Biju
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