linux-kernel - [PATCH v3 0/2] iommu: Avoid setting C-bit for MMIO addresses

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Message-ID:
 <SI2PR01MB439337D5513729BAC122F526DCCDA@SI2PR01MB4393.apcprd01.prod.exchangelabs.com>
Date: Thu, 13 Nov 2025 23:54:05 +0800
From: Wei Wang <wei.w.wang@...mail.com>
To: alex@...zbot.org,
	jgg@...dia.com,
	thomas.lendacky@....com,
	vasant.hegde@....com,
	suravee.suthikulpanit@....com,
	joro@...tes.org
Cc: aik@....com,
	kevin.tian@...el.com,
	wei.w.wang@...mail.com,
	linux-kernel@...r.kernel.org,
	iommu@...ts.linux.dev
Subject: [PATCH v3 0/2] iommu: Avoid setting C-bit for MMIO addresses

AMD APM specifies that any pages corresponding to MMIO addresses must be
configured with the C-bit clear. The current iommu implementation sets
the C-bit on all PTEs in the IOMMU page tables. This is incorrect for PTEs
backed by MMIO, and can break PCIe peer-to-peer communication when IOVA is
used. Fix this by avoiding the C-bit for MMIO-backed mappings.

v2->v3 changes:
- re-implement the iommu part based on the iommu tree which has the
  iommupt patches merged.
  v2 link: https://lkml.org/lkml/2025/11/3/878

v1->v2 changes:
- 1 used page_is_ram() in the AMD IOMMU driver to detect non-RAM
  addresses, avoiding changes to upper-layer callers (vfio and iommufd).
  v2 instead lets upper layers explicitly indicate MMIO mappings via the
  IOMMU_MMIO prot flag. This avoids the potential overhead of
  page_is_ram(). (suggested by Jason Gunthorpe) 
  v1 link: https://lkml.org/lkml/2025/10/23/1211

Wei Wang (2):
  iommupt: Do not set C-bit on MMIO backed PTEs
  vfio/type1: Set IOMMU_MMIO in dma->prot for MMIO-backed addresses

 drivers/iommu/generic_pt/fmt/amdv1.h  |  3 ++-
 drivers/iommu/generic_pt/fmt/x86_64.h |  3 ++-
 drivers/vfio/vfio_iommu_type1.c       | 13 ++++++++-----
 3 files changed, 12 insertions(+), 7 deletions(-)

base-commit: d22ff9a783a792263baca22f80a64cfc7ec319ea
-- 
2.51.1