linux-kernel - Re: [PATCH] x86/events/intel/cstate: Add Pantherlake support

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Message-ID: <6e84a532-5d30-487f-b849-84893ac2a652@intel.com>
Date: Thu, 13 Nov 2025 10:20:31 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: "Kumar, Kaushlendra" <kaushlendra.kumar@...el.com>,
 "mingo@...hat.com" <mingo@...hat.com>, "acme@...nel.org" <acme@...nel.org>,
 "namhyung@...nel.org" <namhyung@...nel.org>,
 "jolsa@...nel.org" <jolsa@...nel.org>,
 "Hunter, Adrian" <adrian.hunter@...el.com>, "bp@...en8.de" <bp@...en8.de>,
 "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
 "x86@...nel.org" <x86@...nel.org>
Cc: "linux-perf-users@...r.kernel.org" <linux-perf-users@...r.kernel.org>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86/events/intel/cstate: Add Pantherlake support

On 11/12/25 20:05, Kumar, Kaushlendra wrote:
> On 11/12/25, [Reviewer Name] wrote:
>> On 11/12/25 01:00, Kaushlendra Kumar wrote:
>>> It supports the same C-state residency counters as
>>> Lunarlake.This enables monitoring of C1, C6, C7 core states and
>>> C2,C3,C6,C10 package states residency counters on Pantherlake
>>> platforms.
>> 
>> Is this actually documented? Or is there just a smoke-filled room
>> at Intel somewhere where this is decided?
> 
> Good point. Baseline for Pantherlake is Lunarlake with respect to C
> states. It is documented in internal documents. This approach is
> consistent with similar implementations throughout the kernel
> codebase for related CPU families.

It needs to be publicly documented somewhere. It doesn't have to be
fancy: a web page or white paper would be fine.

I know it's been allowed to slide up until now. But, according to[1]:

	We (Intel) continuously improve, enabling us to be more curious,
	bold and innovative.

So, can we try to improve this, please?

...>> Also, why *can't* this just be enumerated?
> 
> Could you clarify what you mean by "enumerated"? Are you suggesting:
> 1. Runtime detection instead of static matching?
> 2. A different approach to CPU model matching?
> 3. Something else?
> 
> The current approach follows the established pattern for other Intel 
> CPU models in this driver. If there's a preferred alternative approach, 
> I'm happy to implement it.
Your patch effectively says:

	PTL supports C10 package states residency counters

(among others of course). Why can't there be a bit in CPUID or an MSR
somewhere that, when set, means the same thing? That way, we don't have
to keep patching the kernel every time there's a new CPU model.

I guess in general PMU things haven't been architectural. But this seems
like something that wouldn't be too hard for the CPU itself to enumerate
to software.

1.
https://www.intel.com/content/www/us/en/corporate-responsibility/our-values.html