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Message-ID: <b76fe2d5-d50e-47e2-b9ba-3686316e1c76@intel.com>
Date: Thu, 13 Nov 2025 15:20:35 -0800
From: "Chang S. Bae" <chang.seok.bae@...el.com>
To: Paolo Bonzini <pbonzini@...hat.com>, <kvm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: <seanjc@...gle.com>, <chao.gao@...el.com>, <zhao1.liu@...el.com>
Subject: Re: [PATCH RFC v1 07/20] KVM: nVMX: Support the extended instruction
info field
On 11/11/2025 9:48 AM, Paolo Bonzini wrote:
>
> but here you must not check XCR0, the extended instruction information
> field is always available. The spec says "A non-Intel® APX enabled VMM
> is free to continue using the legacy definition of the field, since lack
> of Intel® APX enabling will guarantee that regIDs are only 4-bits,
> maximum" but you can also use the extended instruction information field
> if you want. So, I'd make this also static_cpu_has(X86_FEATURE_APX).
I just got confirmation from the hardware folks. The CPUID enumeration
alone is sufficient to indicate the presence and usability of the
extended instruction information field, regardless of the XCR0 state.
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