linux-kernel - Re: [PATCH 5/5] ARM: dts: lpc32xx: update #address-cells of arm,pl175 to 2

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Message-ID: <eb9fa1ab-07d7-4f9d-add4-e6fff015ff44@mleia.com>
Date: Fri, 14 Nov 2025 01:44:04 +0200
From: Vladimir Zapolskiy <vz@...ia.com>
To: Frank Li <Frank.Li@....com>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Piotr Wojtaszczyk <piotr.wojtaszczyk@...esys.com>,
 "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
 <devicetree@...r.kernel.org>,
 "moderated list:ARM/LPC32XX SOC SUPPORT"
 <linux-arm-kernel@...ts.infradead.org>,
 open list <linux-kernel@...r.kernel.org>
Cc: imx@...ts.linux.dev
Subject: Re: [PATCH 5/5] ARM: dts: lpc32xx: update #address-cells of arm,pl175
 to 2

Hi Frank.

On 10/29/25 22:28, Frank Li wrote:
> Change #address-cells of arm,pl175 to 2 to fix below CHECK_DTBS warnings:
>    arm/boot/dts/nxp/lpc/lpc3250-ea3250.dtb: memory-controller@...80000 (arm,pl175): #address-cells: 2 was expected
>          from schema $id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
> 
> Signed-off-by: Frank Li <Frank.Li@....com>
> ---
>   arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
> index 77f210a2152dc..0249a1838ee0d 100644
> --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
> +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
> @@ -155,7 +155,7 @@ emc: memory-controller@...80000 {
>   			reg = <0x31080000 0x1000>;
>   			clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
>   			clock-names = "mpmcclk", "apb_pclk";
> -			#address-cells = <1>;
> +			#address-cells = <2>;
>   			#size-cells = <1>;
>   
>   			ranges = <0 0xe0000000 0x01000000>,

Recently you've made a conversion to YAML for arm,pl17x memory controllers
and now this warning is reported - and by the way I believe and it's
opposite to the commit message, the warning is not reported in the upstream,
because lpc3250-ea3250.dts does not enable the controller.

I wonder and let me ask you, why two address cells are needed here?

My default preference is to get one address cell for NOR flash ICs, and
I'd suggest to make a change to the dt binding of the controller.

-- 
Best wishes,
Vladimir