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Message-ID: <20251113032040.1994090-39-irogers@google.com>
Date: Wed, 12 Nov 2025 19:20:26 -0800
From: Ian Rogers <irogers@...gle.com>
To: Adrian Hunter <adrian.hunter@...el.com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>, Benjamin Gray <bgray@...ux.ibm.com>,
Caleb Biggers <caleb.biggers@...el.com>, Edward Baker <edward.baker@...el.com>,
Ian Rogers <irogers@...gle.com>, Ingo Molnar <mingo@...hat.com>,
James Clark <james.clark@...aro.org>, Jing Zhang <renyu.zj@...ux.alibaba.com>,
Jiri Olsa <jolsa@...nel.org>, John Garry <john.g.garry@...cle.com>, Leo Yan <leo.yan@....com>,
Namhyung Kim <namhyung@...nel.org>, Perry Taylor <perry.taylor@...el.com>,
Peter Zijlstra <peterz@...radead.org>, Samantha Alt <samantha.alt@...el.com>,
Sandipan Das <sandipan.das@....com>, Thomas Falcon <thomas.falcon@...el.com>,
Weilin Wang <weilin.wang@...el.com>, Xu Yang <xu.yang_2@....com>, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org
Subject: [PATCH v8 38/52] perf jevents: Add load store breakdown metrics ldst
for Intel
Give breakdown of number of instructions. Use the counter mask (cmask)
to show the number of cycles taken to retire the instructions.
Signed-off-by: Ian Rogers <irogers@...gle.com>
---
tools/perf/pmu-events/intel_metrics.py | 87 +++++++++++++++++++++++++-
1 file changed, 86 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events/intel_metrics.py
index d190d97f4aff..19a284b4c520 100755
--- a/tools/perf/pmu-events/intel_metrics.py
+++ b/tools/perf/pmu-events/intel_metrics.py
@@ -8,7 +8,7 @@ import re
from typing import Optional
from metric import (d_ratio, has_event, max, CheckPmu, Event, JsonEncodeMetric,
JsonEncodeMetricGroupDescriptions, Literal, LoadEvents,
- Metric, MetricGroup, MetricRef, Select)
+ Metric, MetricConstraint, MetricGroup, MetricRef, Select)
# Global command line arguments.
_args = None
@@ -525,6 +525,90 @@ def IntelSwpf() -> Optional[MetricGroup]:
], description="Software prefetch instruction breakdown")
+def IntelLdSt() -> Optional[MetricGroup]:
+ if _args.model in [
+ "bonnell",
+ "nehalemep",
+ "nehalemex",
+ "westmereep-dp",
+ "westmereep-sp",
+ "westmereex",
+ ]:
+ return None
+ LDST_LD = Event("MEM_INST_RETIRED.ALL_LOADS", "MEM_UOPS_RETIRED.ALL_LOADS")
+ LDST_ST = Event("MEM_INST_RETIRED.ALL_STORES",
+ "MEM_UOPS_RETIRED.ALL_STORES")
+ LDST_LDC1 = Event(f"{LDST_LD.name}/cmask=1/")
+ LDST_STC1 = Event(f"{LDST_ST.name}/cmask=1/")
+ LDST_LDC2 = Event(f"{LDST_LD.name}/cmask=2/")
+ LDST_STC2 = Event(f"{LDST_ST.name}/cmask=2/")
+ LDST_LDC3 = Event(f"{LDST_LD.name}/cmask=3/")
+ LDST_STC3 = Event(f"{LDST_ST.name}/cmask=3/")
+ ins = Event("instructions")
+ LDST_CYC = Event("CPU_CLK_UNHALTED.THREAD",
+ "CPU_CLK_UNHALTED.CORE_P",
+ "CPU_CLK_UNHALTED.THREAD_P")
+ LDST_PRE = None
+ try:
+ LDST_PRE = Event("LOAD_HIT_PREFETCH.SWPF", "LOAD_HIT_PRE.SW_PF")
+ except:
+ pass
+ LDST_AT = None
+ try:
+ LDST_AT = Event("MEM_INST_RETIRED.LOCK_LOADS")
+ except:
+ pass
+ cyc = LDST_CYC
+
+ ld_rate = d_ratio(LDST_LD, interval_sec)
+ st_rate = d_ratio(LDST_ST, interval_sec)
+ pf_rate = d_ratio(LDST_PRE, interval_sec) if LDST_PRE else None
+ at_rate = d_ratio(LDST_AT, interval_sec) if LDST_AT else None
+
+ ldst_ret_constraint = MetricConstraint.GROUPED_EVENTS
+ if LDST_LD.name == "MEM_UOPS_RETIRED.ALL_LOADS":
+ ldst_ret_constraint = MetricConstraint.NO_GROUP_EVENTS_NMI
+
+ return MetricGroup("lpm_ldst", [
+ MetricGroup("lpm_ldst_total", [
+ Metric("lpm_ldst_total_loads", "Load/store instructions total loads",
+ ld_rate, "loads"),
+ Metric("lpm_ldst_total_stores", "Load/store instructions total stores",
+ st_rate, "stores"),
+ ]),
+ MetricGroup("lpm_ldst_prcnt", [
+ Metric("lpm_ldst_prcnt_loads", "Percent of all instructions that are loads",
+ d_ratio(LDST_LD, ins), "100%"),
+ Metric("lpm_ldst_prcnt_stores", "Percent of all instructions that are stores",
+ d_ratio(LDST_ST, ins), "100%"),
+ ]),
+ MetricGroup("lpm_ldst_ret_lds", [
+ Metric("lpm_ldst_ret_lds_1", "Retired loads in 1 cycle",
+ d_ratio(max(LDST_LDC1 - LDST_LDC2, 0), cyc), "100%",
+ constraint=ldst_ret_constraint),
+ Metric("lpm_ldst_ret_lds_2", "Retired loads in 2 cycles",
+ d_ratio(max(LDST_LDC2 - LDST_LDC3, 0), cyc), "100%",
+ constraint=ldst_ret_constraint),
+ Metric("lpm_ldst_ret_lds_3", "Retired loads in 3 or more cycles",
+ d_ratio(LDST_LDC3, cyc), "100%"),
+ ]),
+ MetricGroup("lpm_ldst_ret_sts", [
+ Metric("lpm_ldst_ret_sts_1", "Retired stores in 1 cycle",
+ d_ratio(max(LDST_STC1 - LDST_STC2, 0), cyc), "100%",
+ constraint=ldst_ret_constraint),
+ Metric("lpm_ldst_ret_sts_2", "Retired stores in 2 cycles",
+ d_ratio(max(LDST_STC2 - LDST_STC3, 0), cyc), "100%",
+ constraint=ldst_ret_constraint),
+ Metric("lpm_ldst_ret_sts_3", "Retired stores in 3 more cycles",
+ d_ratio(LDST_STC3, cyc), "100%"),
+ ]),
+ Metric("lpm_ldst_ld_hit_swpf", "Load hit software prefetches per second",
+ pf_rate, "swpf/s") if pf_rate else None,
+ Metric("lpm_ldst_atomic_lds", "Atomic loads per second",
+ at_rate, "loads/s") if at_rate else None,
+ ], description="Breakdown of load/store instructions")
+
+
def main() -> None:
global _args
@@ -556,6 +640,7 @@ def main() -> None:
Tsx(),
IntelBr(),
IntelL2(),
+ IntelLdSt(),
IntelPorts(),
IntelSwpf(),
])
--
2.51.2.1041.gc1ab5b90ca-goog
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