linux-kernel - RE: [PATCH] x86/events/intel/cstate: Add Pantherlake support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <LV3PR11MB87682D759248CA310546261CF5CDA@LV3PR11MB8768.namprd11.prod.outlook.com>
Date: Thu, 13 Nov 2025 04:05:40 +0000
From: "Kumar, Kaushlendra" <kaushlendra.kumar@...el.com>
To: "Hansen, Dave" <dave.hansen@...el.com>, "mingo@...hat.com"
	<mingo@...hat.com>, "acme@...nel.org" <acme@...nel.org>,
	"namhyung@...nel.org" <namhyung@...nel.org>, "jolsa@...nel.org"
	<jolsa@...nel.org>, "Hunter, Adrian" <adrian.hunter@...el.com>,
	"bp@...en8.de" <bp@...en8.de>, "dave.hansen@...ux.intel.com"
	<dave.hansen@...ux.intel.com>, "x86@...nel.org" <x86@...nel.org>
CC: "linux-perf-users@...r.kernel.org" <linux-perf-users@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] x86/events/intel/cstate: Add Pantherlake support

On 11/12/25, [Reviewer Name] wrote:
> On 11/12/25 01:00, Kaushlendra Kumar wrote:
> > It supports the same C-state residency counters as Lunarlake.This 
> > enables monitoring of C1, C6, C7 core states and C2,C3,C6,C10 package 
> > states residency counters on Pantherlake platforms.
> 
> Is this actually documented? Or is there just a smoke-filled room at 
> Intel somewhere where this is decided?

Good point. Baseline for Pantherlake is Lunarlake with respect to C states. It is documented in internal documents. This approach is consistent with similar implementations 
throughout the kernel codebase for related CPU families.

> > @@ -41,7 +41,7 @@
> >   *	MSR_CORE_C1_RES: CORE C1 Residency Counter
> >   *			 perf code: 0x00
> >   *			 Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
> > - *					  MTL,SRF,GRR,ARL,LNL
> > + *					  MTL,SRF,GRR,ARL,LNL,PTL
> 
> Could we get rid of these, please?
> 
> Folks can 100% figure this out from the data structures themselves.
> Unless there's a compelling reason, this is pure churn.

Agreed. These comments are indeed redundant. 
If we all agree, I'll remove those.

> > @@ -652,6 +653,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
> >  	X86_MATCH_VFM(INTEL_ARROWLAKE_H,	&adl_cstates),
> >  	X86_MATCH_VFM(INTEL_ARROWLAKE_U,	&adl_cstates),
> >  	X86_MATCH_VFM(INTEL_LUNARLAKE_M,	&lnl_cstates),
> > +	X86_MATCH_VFM(INTEL_PANTHERLAKE_L,	&lnl_cstates),
> >  	{ },
> >  };
> >  MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
> 
> Also, why *can't* this just be enumerated?

Could you clarify what you mean by "enumerated"? Are you suggesting:
1. Runtime detection instead of static matching?
2. A different approach to CPU model matching?
3. Something else?

The current approach follows the established pattern for other Intel 
CPU models in this driver. If there's a preferred alternative approach, 
I'm happy to implement it.