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Message-ID: <CANAwSgQcMDXitA2RLbFsD_v2KoOQMcHywxcxNs-ab-O2JddAuQ@mail.gmail.com>
Date: Thu, 13 Nov 2025 10:46:59 +0530
From: Anand Moon <linux.amoon@...il.com>
To: Manivannan Sadhasivam <mani@...nel.org>
Cc: Lukas Wunner <lukas@...ner.de>,
Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>, andersson@...nel.org, robh@...nel.org,
manivannan.sadhasivam@...aro.org, krzk@...nel.org, helgaas@...nel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
lpieralisi@...nel.org, kw@...ux.com, conor+dt@...nel.org,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree-spec@...r.kernel.org, quic_vbadigan@...cinc.com
Subject: Re: [PATCH v2] schemas: pci: Document PCIe T_POWER_ON
Hi Manivannan
On Thu, 13 Nov 2025 at 10:01, Manivannan Sadhasivam <mani@...nel.org> wrote:
>
> On Mon, Nov 10, 2025 at 01:41:45PM +0100, Lukas Wunner wrote:
> > On Mon, Nov 10, 2025 at 04:59:47PM +0530, Krishna Chaitanya Chundru wrote:
> > > From PCIe r6, sec 5.5.4 & Table 5-11 in sec 5.5.5 T_POWER_ON is the
> >
> > Please use the latest spec version as reference, i.e. PCIe r7.0.
> >
> > > minimum amount of time(in us) that each component must wait in L1.2.Exit
> > > after sampling CLKREQ# asserted before actively driving the interface to
> > > ensure no device is ever actively driving into an unpowered component and
> > > these values are based on the components and AC coupling capacitors used
> > > in the connection linking the two components.
> > >
> > > This property should be used to indicate the T_POWER_ON for each Root Port.
> >
> > What's the difference between this property and the Port T_POWER_ON_Scale
> > and T_POWER_ON_Value in the L1 PM Substates Capabilities Register?
> >
> > Why do you need this in the device tree even though it's available
> > in the register?
> >
>
> Someone needs to program these registers. In the x86 world, BIOS will do it
> happily, but in devicetree world, OS has to do it. And since this is a platform
> specific value, this is getting passed from devicetree.
>
According to the RK3588 TRM Part 2, the DSP_PCIE_L1SUB_CAPABILITY_REG (0x4)
It is a commonly configurable parameter, It can be tuned on for the
Rockchip platform.
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
>
Thanks
-Anand
I could not apply this patch
$ git am ./v2_20251110_krishna_chundru_schemas_pci_document_pcie_t_power_on.mbx
Applying: schemas: pci: Document PCIe T_POWER_ON
error: dtschema/schemas/pci/pci-bus-common.yaml: does not exist in index
Patch failed at 0001 schemas: pci: Document PCIe T_POWER_ON
hint: Use 'git am --show-current-patch=diff' to see the failed patch
hint: When you have resolved this problem, run "git am --continue".
hint: If you prefer to skip this patch, run "git am --skip" instead.
hint: To restore the original branch and stop patching, run "git am --abort".
hint: Disable this message with "git config set advice.mergeConflict false"
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