linux-kernel - [PATCH V15 6/6] dt-bindings: riscv: Add Svrsw60t59b extension description

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Message-Id: <20251113072806.795029-7-zhangchunyan@iscas.ac.cn>
Date: Thu, 13 Nov 2025 15:28:06 +0800
From: Chunyan Zhang <zhangchunyan@...as.ac.cn>
To: Andrew Morton <akpm@...ux-foundation.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Alexander Viro <viro@...iv.linux.org.uk>
Cc: linux-mm@...ck.org,
	Peter Xu <peterx@...hat.com>,
	Arnd Bergmann <arnd@...db.de>,
	David Hildenbrand <david@...hat.com>,
	Lorenzo Stoakes <lorenzo.stoakes@...cle.com>,
	"Liam R . Howlett" <Liam.Howlett@...cle.com>,
	Vlastimil Babka <vbabka@...e.cz>,
	Mike Rapoport <rppt@...nel.org>,
	Suren Baghdasaryan <surenb@...gle.com>,
	Michal Hocko <mhocko@...e.com>,
	Axel Rasmussen <axelrasmussen@...gle.com>,
	Yuanchu Xie <yuanchu@...gle.com>,
	linux-riscv@...ts.infradead.org,
	Albert Ou <aou@...s.berkeley.edu>,
	Alexandre Ghiti <alex@...ti.fr>,
	devicetree@...r.kernel.org,
	Conor Dooley <conor@...nel.org>,
	Deepak Gupta <debug@...osinc.com>,
	Ved Shanbhogue <ved@...osinc.com>,
	linux-fsdevel@...r.kernel.org,
	Christian Brauner <brauner@...nel.org>,
	Jan Kara <jack@...e.cz>,
	linux-kernel@...r.kernel.org,
	Chunyan Zhang <zhang.lyra@...il.com>
Subject: [PATCH V15 6/6] dt-bindings: riscv: Add Svrsw60t59b extension description

Add description for the Svrsw60t59b extension (PTE Reserved for SW
bits 60:59) extension which was ratified recently in
riscv-non-isa/riscv-iommu.

Acked-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Chunyan Zhang <zhangchunyan@...as.ac.cn>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 543ac94718e8..194ef4754452 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -217,6 +217,12 @@ properties:
             memory types as ratified in the 20191213 version of the privileged
             ISA specification.
 
+        - const: svrsw60t59b
+          description:
+            The Svrsw60t59b extension for providing two more bits[60:59] to
+            PTE/PMD entry as ratified at commit 28bde925e7a7 ("PTE Reserved
+            for SW bits 60:59") of riscv-non-isa/riscv-iommu.
+
         - const: svvptc
           description:
             The standard Svvptc supervisor-level extension for
-- 
2.34.1