linux-kernel - Re: [PATCH v22 1/4] dt-bindings: i2c: Split AST2600 binding into a new YAML

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Message-ID: <20251113-waxbill-of-awesome-fame-8a84d1@kuoka>
Date: Thu, 13 Nov 2025 09:00:49 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Ryan Chen <ryan_chen@...eedtech.com>
Cc: bmc-sw@...eedtech.com, benh@...nel.crashing.org, joel@....id.au, 
	andi.shyti@...nel.org, jk@...econstruct.com.au, robh@...nel.org, krzk+dt@...nel.org, 
	conor+dt@...nel.org, andrew@...econstruct.com.au, p.zabel@...gutronix.de, 
	andriy.shevchenko@...ux.intel.com, naresh.solanki@...ements.com, linux-i2c@...r.kernel.org, 
	openbmc@...ts.ozlabs.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-aspeed@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v22 1/4] dt-bindings: i2c: Split AST2600 binding into a
 new YAML

On Wed, Nov 12, 2025 at 04:56:46PM +0800, Ryan Chen wrote:
> The AST2600 I2C controller introduces a completely new register
> map and Separate control/target register sets, unlike the mixed
> layout used in AST2400/AST2500.
> 
> In addition, at new AST2600 configuration registers and transfer
> modes require new DT properties, which are incompatible with
> existing bindings. Therefore, this creates a dedicated binding
> file for AST2600 to properly describe these new hardware
> capabilities.
> 
> A subsequent change will modify this new binding to properly
> describe the AST2600 hardware.
> 
> The example section updated to reflect the actual AST2600 SoC
> register layout and interrupt configuration.
> Reference: aspeed-g6.dtsi (lines 885-897)
> 
> -I2C bus and buffeset address offsets
>  - AST2600 I2C controller register base starts from 0x80, and the
>    buffer region is located at 0xc00, as defined in AST2600 SOC
>    register map.
> 
> -Interrupt configuration
>  - AST2600 U2C controller are connected to ARM GIC interrupt
>    controller rather than the legacy internal interrupt controller.
> 
> Signed-off-by: Ryan Chen <ryan_chen@...eedtech.com>
> ---
>  .../bindings/i2c/aspeed,ast2600-i2c.yaml      | 67 +++++++++++++++++++
>  .../devicetree/bindings/i2c/aspeed,i2c.yaml   |  3 +-
>  2 files changed, 68 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml
> 
> diff --git a/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml
> new file mode 100644
> index 000000000000..e6ed84c53639
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/i2c/aspeed,ast2600-i2c.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ASPEED I2C on the AST26XX SoCs
> +
> +maintainers:
> +  - Ryan Chen <ryan_chen@...eedtech.com>
> +
> +allOf:
> +  - $ref: /schemas/i2c/i2c-controller.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - aspeed,ast2600-i2c-bus
> +
> +  reg:
> +    minItems: 1
> +    maxItems: 2
> +    description:
> +      The first region covers the controller registers.
> +      The optional second region covers the controller's buffer space.

1. List the items instead. We discussed this already and this had
correct format in the past and now it is getting to some odd style. Why?

2. How region can be optional? Device either has it or does not have it.
Please explain me how one, same SoC has optional IO address space? I
asked to explain WHY this is flexible.

You never replied.

NAK, we are discussing same over and over again. I am not reviewing the
rest. Go to previous versions and read the feedback again.

Best regards,
Krzysztof