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Message-ID: <20251113085332.89688-3-chin-ting_kuo@aspeedtech.com>
Date: Thu, 13 Nov 2025 16:53:30 +0800
From: Chin-Ting Kuo <chin-ting_kuo@...eedtech.com>
To: <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<joel@....id.au>, <andrew@...econstruct.com.au>, <clg@...d.org>,
<clg@...hat.com>, <broonie@...nel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-aspeed@...ts.ozlabs.org>,
<linux-kernel@...r.kernel.org>, <openbmc@...ts.ozlabs.org>,
<linux-spi@...r.kernel.org>, <BMC-SW@...eedtech.com>
Subject: [PATCH 2/4] spi: aspeed: Enable Quad SPI mode for page program
Ensure the controller switches to quad I/O mode when
spi-tx-bus-width dts property is 4 and the Quad SPI program
opcode (32h or 34h) is used. Without this change, high-bit
data will be lost during page programming.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@...eedtech.com>
---
drivers/spi/spi-aspeed-smc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 179c47ffbfeb..4163632fed8b 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -263,11 +263,15 @@ static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
const struct spi_mem_op *op)
{
int ret;
+ int io_mode = aspeed_spi_get_io_mode(op);
aspeed_spi_start_user(chip);
ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
if (ret < 0)
goto stop_user;
+
+ aspeed_spi_set_io_mode(chip, io_mode);
+
aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
stop_user:
aspeed_spi_stop_user(chip);
--
2.34.1
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