| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20251114160954.GJ3568724@e132581.arm.com>
Date: Fri, 14 Nov 2025 16:09:54 +0000
From: Leo Yan <leo.yan@....com>
To: James Clark <james.clark@...aro.org>
Cc: Suzuki K Poulose <suzuki.poulose@....com>,
Mike Leach <mike.leach@...aro.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jonathan Corbet <corbet@....net>, coresight@...ts.linaro.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-doc@...r.kernel.org
Subject: Re: [PATCH v4 09/13] coresight: Interpret ETMv4 config with
ATTR_CFG_GET_FLD()
On Wed, Nov 12, 2025 at 03:22:15PM +0000, James Clark wrote:
> Remove hard coded bitfield extractions and shifts and replace with
> ATTR_CFG_GET_FLD().
>
> ETM4_CFG_BIT_BB was defined to give the register bit positions to
> userspace, TRCCONFIGR_BB should be used in the kernel so replace it.
>
> Signed-off-by: James Clark <james.clark@...aro.org>
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 44 ++++++++++------------
> 1 file changed, 19 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 380a7840adb8..1aa0357a5ce7 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -29,6 +29,7 @@
> #include <linux/seq_file.h>
> #include <linux/uaccess.h>
> #include <linux/perf_event.h>
> +#include <linux/perf/arm_pmu.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> @@ -789,17 +790,17 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> goto out;
>
> /* Go from generic option to ETMv4 specifics */
> - if (attr->config & BIT(ETM_OPT_CYCACC)) {
> + if (ATTR_CFG_GET_FLD(attr, cycacc)) {
> config->cfg |= TRCCONFIGR_CCI;
> /* TRM: Must program this for cycacc to work */
> - cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK;
> + cc_threshold = ATTR_CFG_GET_FLD(attr, cc_threshold);
> if (!cc_threshold)
> cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;
> if (cc_threshold < drvdata->ccitmin)
> cc_threshold = drvdata->ccitmin;
> config->ccctlr = cc_threshold;
> }
> - if (attr->config & BIT(ETM_OPT_TS)) {
> + if (ATTR_CFG_GET_FLD(attr, timestamp)) {
> /*
> * Configure timestamps to be emitted at regular intervals in
> * order to correlate instructions executed on different CPUs
> @@ -819,17 +820,17 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> }
>
> /* Only trace contextID when runs in root PID namespace */
> - if ((attr->config & BIT(ETM_OPT_CTXTID)) &&
> + if (ATTR_CFG_GET_FLD(attr, contextid1) &&
> task_is_in_init_pid_ns(current))
> /* bit[6], Context ID tracing bit */
> config->cfg |= TRCCONFIGR_CID;
>
> /*
> - * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
> - * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the
> - * kernel is not running in EL2.
> + * If set bit contextid2 in perf config, this asks to trace VMID for
> + * recording CONTEXTIDR_EL2. Do not enable VMID tracing if the kernel
> + * is not running in EL2.
> */
> - if (attr->config & BIT(ETM_OPT_CTXTID2)) {
> + if (ATTR_CFG_GET_FLD(attr, contextid2)) {
> if (!is_kernel_in_hyp_mode()) {
> ret = -EINVAL;
> goto out;
> @@ -840,26 +841,22 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> }
>
> /* return stack - enable if selected and supported */
> - if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
> + if (ATTR_CFG_GET_FLD(attr, retstack) && drvdata->retstack)
> /* bit[12], Return stack enable bit */
> config->cfg |= TRCCONFIGR_RS;
>
> /*
> - * Set any selected configuration and preset.
> - *
> - * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
> - * in the perf attributes defined in coresight-etm-perf.c.
> - * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
> - * A zero configid means no configuration active, preset = 0 means no preset selected.
> + * Set any selected configuration and preset. A zero configid means no
> + * configuration active, preset = 0 means no preset selected.
> */
> - if (attr->config2 & GENMASK_ULL(63, 32)) {
> - cfg_hash = (u32)(attr->config2 >> 32);
> - preset = attr->config & 0xF;
> + if (ATTR_CFG_GET_FLD(attr, configid)) {
> + cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
Nitpick:
cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
if (cfg_hash) {
Then we can avoid a redundant ATTR_CFG_GET_FLD().
Otherwise:
Reviewed-by: Leo Yan <leo.yan@....com>
> + preset = ATTR_CFG_GET_FLD(attr, preset);
> ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
> }
>
> /* branch broadcast - enable if selected and supported */
> - if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
> + if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
> if (!drvdata->trcbb) {
> /*
> * Missing BB support could cause silent decode errors
> @@ -868,7 +865,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> ret = -EINVAL;
> goto out;
> } else {
> - config->cfg |= BIT(ETM4_CFG_BIT_BB);
> + config->cfg |= TRCCONFIGR_BB;
> }
> }
>
> @@ -1104,11 +1101,8 @@ static int etm4_disable_perf(struct coresight_device *csdev,
> return -EINVAL;
>
> etm4_disable_hw(drvdata);
> - /*
> - * The config_id occupies bits 63:32 of the config2 perf event attr
> - * field. If this is non-zero then we will have enabled a config.
> - */
> - if (attr->config2 & GENMASK_ULL(63, 32))
> + /* If configid is non-zero then we will have enabled a config. */
> + if (ATTR_CFG_GET_FLD(attr, configid))
> cscfg_csdev_disable_active_config(csdev);
>
> /*
>
> --
> 2.34.1
>
Powered by blists - more mailing lists