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Message-ID: <20251114-upstream_uboot_properties-v2-1-3784ff668ae0@foss.st.com>
Date: Fri, 14 Nov 2025 18:26:01 +0100
From: Patrice Chotard <patrice.chotard@...s.st.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin
<mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Patrick Delaunay <patrick.delaunay@...s.st.com>
CC: <devicetree@...r.kernel.org>, <linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
Patrice Chotard <patrice.chotard@...s.st.com>
Subject: [PATCH v2 1/6] ARM: dts: stm32: Add boot phase tags for
STMicroelectronics f4 boards
The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.
To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.
Signed-off-by: Patrice Chotard <patrice.chotard@...s.st.com>
---
arch/arm/boot/dts/st/stm32429i-eval.dts | 11 +++++++++++
arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi | 12 ++++++++++++
arch/arm/boot/dts/st/stm32f429-disco.dts | 11 +++++++++++
arch/arm/boot/dts/st/stm32f429.dtsi | 9 +++++++++
arch/arm/boot/dts/st/stm32f469-disco.dts | 12 ++++++++++++
5 files changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts
index afa417b34b25..3b6151fcb070 100644
--- a/arch/arm/boot/dts/st/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/st/stm32429i-eval.dts
@@ -312,6 +312,7 @@ &timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
+ bootph-all;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
@@ -326,6 +327,16 @@ &usart1 {
status = "okay";
};
+&usart1_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
&usbotg_hs {
dr_mode = "host";
phys = <&usbotg_hs_phy>;
diff --git a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
index 3bb812d6399e..bcaed4618738 100644
--- a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
@@ -51,6 +51,7 @@ pinctrl: pinctrl@...20000 {
ranges = <0 0x40020000 0x3000>;
interrupt-parent = <&exti>;
st,syscfg = <&syscfg 0x8>;
+ bootph-all;
gpioa: gpio@...20000 {
gpio-controller;
@@ -60,6 +61,7 @@ gpioa: gpio@...20000 {
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
+ bootph-all;
};
gpiob: gpio@...20400 {
@@ -70,6 +72,7 @@ gpiob: gpio@...20400 {
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
+ bootph-all;
};
gpioc: gpio@...20800 {
@@ -80,6 +83,7 @@ gpioc: gpio@...20800 {
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
+ bootph-all;
};
gpiod: gpio@...20c00 {
@@ -90,6 +94,7 @@ gpiod: gpio@...20c00 {
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
+ bootph-all;
};
gpioe: gpio@...21000 {
@@ -100,6 +105,7 @@ gpioe: gpio@...21000 {
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
+ bootph-all;
};
gpiof: gpio@...21400 {
@@ -110,6 +116,7 @@ gpiof: gpio@...21400 {
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
+ bootph-all;
};
gpiog: gpio@...21800 {
@@ -120,6 +127,7 @@ gpiog: gpio@...21800 {
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
+ bootph-all;
};
gpioh: gpio@...21c00 {
@@ -130,6 +138,7 @@ gpioh: gpio@...21c00 {
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
+ bootph-all;
};
gpioi: gpio@...22000 {
@@ -140,6 +149,7 @@ gpioi: gpio@...22000 {
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
+ bootph-all;
};
gpioj: gpio@...22400 {
@@ -150,6 +160,7 @@ gpioj: gpio@...22400 {
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
+ bootph-all;
};
gpiok: gpio@...22800 {
@@ -160,6 +171,7 @@ gpiok: gpio@...22800 {
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
+ bootph-all;
};
usart1_pins_a: usart1-0 {
diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts
index a3cb4aabdd5a..39a80a9caa5f 100644
--- a/arch/arm/boot/dts/st/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/st/stm32f429-disco.dts
@@ -209,6 +209,7 @@ &timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
+ bootph-all;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
@@ -223,6 +224,16 @@ &usart1 {
status = "okay";
};
+&usart1_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
&usbotg_hs {
compatible = "st,stm32f4x9-fsotg";
dr_mode = "host";
diff --git a/arch/arm/boot/dts/st/stm32f429.dtsi b/arch/arm/boot/dts/st/stm32f429.dtsi
index ad91b74ddd0d..51c931f7b9d5 100644
--- a/arch/arm/boot/dts/st/stm32f429.dtsi
+++ b/arch/arm/boot/dts/st/stm32f429.dtsi
@@ -54,16 +54,20 @@ / {
#size-cells = <1>;
clocks {
+ bootph-all;
+
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
+ bootph-all;
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
+ bootph-all;
};
clk_lsi: clk-lsi {
@@ -76,10 +80,12 @@ clk_i2s_ckin: i2s-ckin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
+ bootph-all;
};
};
soc {
+ bootph-all;
romem: efuse@...f7800 {
compatible = "st,stm32f4-otp";
reg = <0x1fff7800 0x400>;
@@ -580,6 +586,7 @@ syscfg: syscon@...13800 {
compatible = "st,stm32-syscfg", "syscon";
reg = <0x40013800 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>;
+ bootph-all;
};
exti: interrupt-controller@...13c00 {
@@ -666,6 +673,7 @@ spi6: spi@...15400 {
pwrcfg: power-config@...07000 {
compatible = "st,stm32-power-config", "syscon";
reg = <0x40007000 0x400>;
+ bootph-all;
};
ltdc: display-controller@...16800 {
@@ -694,6 +702,7 @@ rcc: rcc@...23800 {
st,syscfg = <&pwrcfg>;
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
assigned-clock-rates = <1000000>;
+ bootph-all;
};
dma1: dma-controller@...26000 {
diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts
index 8a4f8ddd083d..de025a385e9e 100644
--- a/arch/arm/boot/dts/st/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/st/stm32f469-disco.dts
@@ -169,6 +169,7 @@ dsi_panel_in: endpoint {
};
<dc {
+ bootph-all;
status = "okay";
port {
@@ -225,6 +226,7 @@ &timers5 {
/* Override timer5 to act as clockevent */
compatible = "st,stm32-timer";
interrupts = <50>;
+ bootph-all;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
@@ -239,6 +241,16 @@ &usart3 {
status = "okay";
};
+&usart3_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
&usbotg_fs {
dr_mode = "host";
pinctrl-0 = <&usbotg_fs_pins_a>;
--
2.43.0
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