| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20251114-upstream_uboot_properties-v2-6-3784ff668ae0@foss.st.com>
Date: Fri, 14 Nov 2025 18:26:06 +0100
From: Patrice Chotard <patrice.chotard@...s.st.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin
<mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Patrick Delaunay <patrick.delaunay@...s.st.com>
CC: <devicetree@...r.kernel.org>, <linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
Patrice Chotard <patrice.chotard@...s.st.com>
Subject: [PATCH v2 6/6] arm64: dts: st: Add boot phase tags for
STMicroelectronics mp2 boards
The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.
To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.
Signed-off-by: Patrice Chotard <patrice.chotard@...s.st.com>
---
arch/arm64/boot/dts/st/stm32mp211.dtsi | 7 +++++++
arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 1 +
arch/arm64/boot/dts/st/stm32mp231.dtsi | 22 ++++++++++++++++++++++
arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 11 +++++++++++
arch/arm64/boot/dts/st/stm32mp251.dtsi | 26 ++++++++++++++++++++++++++
arch/arm64/boot/dts/st/stm32mp255.dtsi | 3 ++-
arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 11 +++++++++++
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 11 +++++++++++
8 files changed, 91 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi
index bf888d60cd4f..81b6a71fc032 100644
--- a/arch/arm64/boot/dts/st/stm32mp211.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi
@@ -50,6 +50,7 @@ firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
+ bootph-all;
};
scmi: scmi {
@@ -57,15 +58,18 @@ scmi: scmi {
#address-cells = <1>;
#size-cells = <0>;
linaro,optee-channel-id = <0>;
+ bootph-all;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
+ bootph-all;
};
scmi_reset: protocol@16 {
reg = <0x16>;
#reset-cells = <1>;
+ bootph-all;
};
};
};
@@ -73,6 +77,7 @@ scmi_reset: protocol@16 {
psci {
compatible = "arm,psci-1.0";
method = "smc";
+ bootph-all;
};
timer {
@@ -92,6 +97,7 @@ soc@0 {
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <2>;
+ bootph-all;
rifsc: bus@...80000 {
compatible = "simple-bus";
@@ -100,6 +106,7 @@ rifsc: bus@...80000 {
dma-ranges;
#address-cells = <1>;
#size-cells = <2>;
+ bootph-all;
usart2: serial@...e0000 {
compatible = "st,stm32h7-uart";
diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts
index 7bdaeaa5ab0f..bc366639744a 100644
--- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts
@@ -45,5 +45,6 @@ &arm_wdt {
};
&usart2 {
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi
index 88e214d395ab..075b4419d3ae 100644
--- a/arch/arm64/boot/dts/st/stm32mp231.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi
@@ -57,6 +57,7 @@ optee: optee {
method = "smc";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ bootph-all;
};
scmi {
@@ -64,15 +65,18 @@ scmi {
#address-cells = <1>;
#size-cells = <0>;
linaro,optee-channel-id = <0>;
+ bootph-all;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
+ bootph-all;
};
scmi_reset: protocol@16 {
reg = <0x16>;
#reset-cells = <1>;
+ bootph-all;
};
scmi_voltd: protocol@17 {
@@ -114,6 +118,7 @@ scmi_vdda18adc: regulator@7 {
psci {
compatible = "arm,psci-1.0";
method = "smc";
+ bootph-all;
cpu0_pd: power-domain-cpu0 {
#power-domain-cells = <0>;
@@ -146,6 +151,7 @@ soc@0 {
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
+ bootph-all;
hpdma: dma-controller@...00000 {
compatible = "st,stm32mp25-dma3";
@@ -223,6 +229,7 @@ rifsc: bus@...80000 {
#address-cells = <1>;
#size-cells = <1>;
#access-controller-cells = <1>;
+ bootph-all;
i2s2: audio-controller@...b0000 {
compatible = "st,stm32mp25-i2s";
@@ -760,6 +767,7 @@ bsec: efuse@...00000 {
reg = <0x44000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ bootph-all;
part_number_otp@24 {
reg = <0x24 0x4>;
@@ -857,6 +865,7 @@ rcc: clock-controller@...00000 {
<&scmi_clk CK_SCMI_PLL3>,
<&clk_dsi_txbyte>;
access-controllers = <&rifsc 156>;
+ bootph-all;
};
exti1: interrupt-controller@...20000 {
@@ -955,6 +964,7 @@ exti1: interrupt-controller@...20000 {
syscfg: syscon@...30000 {
compatible = "st,stm32mp23-syscfg", "syscon";
reg = <0x44230000 0x10000>;
+ bootph-all;
};
pinctrl: pinctrl@...40000 {
@@ -965,6 +975,7 @@ pinctrl: pinctrl@...40000 {
interrupt-parent = <&exti1>;
st,syscfg = <&exti1 0x60 0xff>;
pins-are-numbered;
+ bootph-all;
gpioa: gpio@...40000 {
reg = <0x0 0x400>;
@@ -974,6 +985,7 @@ gpioa: gpio@...40000 {
#interrupt-cells = <2>;
clocks = <&scmi_clk CK_SCMI_GPIOA>;
st,bank-name = "GPIOA";
+ bootph-all;
status = "disabled";
};
@@ -985,6 +997,7 @@ gpiob: gpio@...50000 {
#interrupt-cells = <2>;
clocks = <&scmi_clk CK_SCMI_GPIOB>;
st,bank-name = "GPIOB";
+ bootph-all;
status = "disabled";
};
@@ -996,6 +1009,7 @@ gpioc: gpio@...60000 {
#interrupt-cells = <2>;
clocks = <&scmi_clk CK_SCMI_GPIOC>;
st,bank-name = "GPIOC";
+ bootph-all;
status = "disabled";
};
@@ -1007,6 +1021,7 @@ gpiod: gpio@...70000 {
#interrupt-cells = <2>;
clocks = <&scmi_clk CK_SCMI_GPIOD>;
st,bank-name = "GPIOD";
+ bootph-all;
status = "disabled";
};
@@ -1018,6 +1033,7 @@ gpioe: gpio@...80000 {
#interrupt-cells = <2>;
clocks = <&scmi_clk CK_SCMI_GPIOE>;
st,bank-name = "GPIOE";
+ bootph-all;
status = "disabled";
};
@@ -1029,6 +1045,7 @@ gpiof: gpio@...90000 {
#interrupt-cells = <2>;
clocks = <&scmi_clk CK_SCMI_GPIOF>;
st,bank-name = "GPIOF";
+ bootph-all;
status = "disabled";
};
@@ -1040,6 +1057,7 @@ gpiog: gpio@...a0000 {
#interrupt-cells = <2>;
clocks = <&scmi_clk CK_SCMI_GPIOG>;
st,bank-name = "GPIOG";
+ bootph-all;
status = "disabled";
};
@@ -1051,6 +1069,7 @@ gpioh: gpio@...b0000 {
#interrupt-cells = <2>;
clocks = <&scmi_clk CK_SCMI_GPIOH>;
st,bank-name = "GPIOH";
+ bootph-all;
status = "disabled";
};
@@ -1062,6 +1081,7 @@ gpioi: gpio@...c0000 {
#interrupt-cells = <2>;
clocks = <&scmi_clk CK_SCMI_GPIOI>;
st,bank-name = "GPIOI";
+ bootph-all;
status = "disabled";
};
};
@@ -1084,6 +1104,7 @@ pinctrl_z: pinctrl@...00000 {
interrupt-parent = <&exti1>;
st,syscfg = <&exti1 0x60 0xff>;
pins-are-numbered;
+ bootph-all;
gpioz: gpio@...00000 {
reg = <0 0x400>;
@@ -1094,6 +1115,7 @@ gpioz: gpio@...00000 {
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
+ bootph-all;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
index c3e688068223..391494eda5e6 100644
--- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
@@ -130,7 +130,18 @@ &usart2 {
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_idle_pins_a>;
pinctrl-2 = <&usart2_sleep_pins_a>;
+ bootph-all;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
+
+&usart2_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index a8e6e0f77b83..f6576304f42f 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -66,6 +66,7 @@ optee: optee {
method = "smc";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ bootph-all;
};
scmi {
@@ -73,15 +74,18 @@ scmi {
#address-cells = <1>;
#size-cells = <0>;
linaro,optee-channel-id = <0>;
+ bootph-all;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
+ bootph-all;
};
scmi_reset: protocol@16 {
reg = <0x16>;
#reset-cells = <1>;
+ bootph-all;
};
scmi_voltd: protocol@17 {
@@ -142,6 +146,7 @@ v2m0: v2m@...90000 {
psci {
compatible = "arm,psci-1.0";
method = "smc";
+ bootph-all;
CPU_PD0: power-domain-cpu0 {
#power-domain-cells = <0>;
@@ -174,6 +179,7 @@ soc@0 {
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges = <0x0 0x0 0x0 0x80000000>;
+ bootph-all;
hpdma: dma-controller@...00000 {
compatible = "st,stm32mp25-dma3";
@@ -305,6 +311,7 @@ rifsc: bus@...80000 {
#size-cells = <1>;
#access-controller-cells = <1>;
ranges;
+ bootph-all;
timers2: timer@...00000 {
compatible = "st,stm32mp25-timers";
@@ -1569,6 +1576,7 @@ trigger@4 {
};
ltdc: display-controller@...10000 {
+ bootph-all;
compatible = "st,stm32mp251-ltdc";
reg = <0x48010000 0x400>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
@@ -1577,6 +1585,7 @@ ltdc: display-controller@...10000 {
clock-names = "lcd", "bus";
resets = <&rcc LTDC_R>;
access-controllers = <&rifsc 80>;
+ bootph-all;
status = "disabled";
};
@@ -1738,6 +1747,7 @@ bsec: efuse@...00000 {
reg = <0x44000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ bootph-all;
part_number_otp@24 {
reg = <0x24 0x4>;
@@ -1842,6 +1852,7 @@ rcc: clock-controller@...00000 {
<&scmi_clk CK_SCMI_PLL3>,
<&clk_dsi_txbyte>;
access-controllers = <&rifsc 156>;
+ bootph-all;
};
exti1: interrupt-controller@...20000 {
@@ -1941,6 +1952,7 @@ syscfg: syscon@...30000 {
compatible = "st,stm32mp25-syscfg", "syscon";
reg = <0x44230000 0x10000>;
#clock-cells = <0>;
+ bootph-all;
};
pinctrl: pinctrl@...40000 {
@@ -1951,6 +1963,7 @@ pinctrl: pinctrl@...40000 {
interrupt-parent = <&exti1>;
st,syscfg = <&exti1 0x60 0xff>;
pins-are-numbered;
+ bootph-all;
gpioa: gpio@...40000 {
gpio-controller;
@@ -1960,6 +1973,7 @@ gpioa: gpio@...40000 {
reg = <0x0 0x400>;
clocks = <&scmi_clk CK_SCMI_GPIOA>;
st,bank-name = "GPIOA";
+ bootph-all;
status = "disabled";
};
@@ -1971,6 +1985,7 @@ gpiob: gpio@...50000 {
reg = <0x10000 0x400>;
clocks = <&scmi_clk CK_SCMI_GPIOB>;
st,bank-name = "GPIOB";
+ bootph-all;
status = "disabled";
};
@@ -1982,6 +1997,7 @@ gpioc: gpio@...60000 {
reg = <0x20000 0x400>;
clocks = <&scmi_clk CK_SCMI_GPIOC>;
st,bank-name = "GPIOC";
+ bootph-all;
status = "disabled";
};
@@ -1993,6 +2009,7 @@ gpiod: gpio@...70000 {
reg = <0x30000 0x400>;
clocks = <&scmi_clk CK_SCMI_GPIOD>;
st,bank-name = "GPIOD";
+ bootph-all;
status = "disabled";
};
@@ -2004,6 +2021,7 @@ gpioe: gpio@...80000 {
reg = <0x40000 0x400>;
clocks = <&scmi_clk CK_SCMI_GPIOE>;
st,bank-name = "GPIOE";
+ bootph-all;
status = "disabled";
};
@@ -2015,6 +2033,7 @@ gpiof: gpio@...90000 {
reg = <0x50000 0x400>;
clocks = <&scmi_clk CK_SCMI_GPIOF>;
st,bank-name = "GPIOF";
+ bootph-all;
status = "disabled";
};
@@ -2026,6 +2045,7 @@ gpiog: gpio@...a0000 {
reg = <0x60000 0x400>;
clocks = <&scmi_clk CK_SCMI_GPIOG>;
st,bank-name = "GPIOG";
+ bootph-all;
status = "disabled";
};
@@ -2037,6 +2057,7 @@ gpioh: gpio@...b0000 {
reg = <0x70000 0x400>;
clocks = <&scmi_clk CK_SCMI_GPIOH>;
st,bank-name = "GPIOH";
+ bootph-all;
status = "disabled";
};
@@ -2048,6 +2069,7 @@ gpioi: gpio@...c0000 {
reg = <0x80000 0x400>;
clocks = <&scmi_clk CK_SCMI_GPIOI>;
st,bank-name = "GPIOI";
+ bootph-all;
status = "disabled";
};
@@ -2059,6 +2081,7 @@ gpioj: gpio@...d0000 {
reg = <0x90000 0x400>;
clocks = <&scmi_clk CK_SCMI_GPIOJ>;
st,bank-name = "GPIOJ";
+ bootph-all;
status = "disabled";
};
@@ -2070,6 +2093,7 @@ gpiok: gpio@...e0000 {
reg = <0xa0000 0x400>;
clocks = <&scmi_clk CK_SCMI_GPIOK>;
st,bank-name = "GPIOK";
+ bootph-all;
status = "disabled";
};
};
@@ -2092,6 +2116,7 @@ pinctrl_z: pinctrl@...00000 {
interrupt-parent = <&exti1>;
st,syscfg = <&exti1 0x60 0xff>;
pins-are-numbered;
+ bootph-all;
gpioz: gpio@...00000 {
gpio-controller;
@@ -2102,6 +2127,7 @@ gpioz: gpio@...00000 {
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
+ bootph-all;
status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi
index 7a598f53a2a0..7b2e07613030 100644
--- a/arch/arm64/boot/dts/st/stm32mp255.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi
@@ -21,6 +21,7 @@ lvds: lvds@...60000 {
resets = <&rcc LVDS_R>;
access-controllers = <&rifsc 84>;
power-domains = <&CLUSTER_PD>;
+ bootph-all;
status = "disabled";
};
@@ -40,4 +41,4 @@ venc: venc@...e0000 {
clocks = <&rcc CK_BUS_VENC>;
access-controllers = <&rifsc 90>;
};
-};
\ No newline at end of file
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
index e718d888ce21..69bac9e719d7 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
@@ -130,7 +130,18 @@ &usart2 {
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_idle_pins_a>;
pinctrl-2 = <&usart2_sleep_pins_a>;
+ bootph-all;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
+
+&usart2_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
index 6e165073f732..307b9692b00a 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -477,11 +477,22 @@ &usart2 {
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_idle_pins_a>;
pinctrl-2 = <&usart2_sleep_pins_a>;
+ bootph-all;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
+&usart2_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
&usart6 {
pinctrl-names = "default", "idle", "sleep";
pinctrl-0 = <&usart6_pins_a>;
--
2.43.0
Powered by blists - more mailing lists