linux-kernel - Re: [PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and host controller

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Message-ID: <20251114060505.GA25077@sventech.com>
Date: Thu, 13 Nov 2025 22:05:05 -0800
From: Johannes Erdfelt <johannes@...felt.com>
To: Alex Elder <elder@...cstar.com>
Cc: dlan@...too.org, robh@...nel.org, krzk+dt@...nel.org,
	conor+dt@...nel.org, vkoul@...nel.org, kishon@...nel.org,
	bhelgaas@...gle.com, lpieralisi@...nel.org, kwilczynski@...nel.org,
	mani@...nel.org, ziyao@...root.org, aurelien@...el32.net,
	mayank.rana@....qualcomm.com, qiang.yu@....qualcomm.com,
	shradha.t@...sung.com, inochiama@...il.com, pjw@...nel.org,
	palmer@...belt.com, aou@...s.berkeley.edu, alex@...ti.fr,
	p.zabel@...gutronix.de, christian.bruel@...s.st.com,
	thippeswamy.havalige@....com, krishna.chundru@....qualcomm.com,
	guodong@...cstar.com, devicetree@...r.kernel.org,
	linux-pci@...r.kernel.org, linux-phy@...ts.infradead.org,
	spacemit@...ts.linux.dev, linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and host controller

On Thu, Nov 13, 2025, Alex Elder <elder@...cstar.com> wrote:
> This series introduces a PHY driver and a PCIe driver to support PCIe
> on the SpacemiT K1 SoC.  The PCIe implementation is derived from a
> Synopsys DesignWare PCIe IP.  The PHY driver supports one combination
> PCIe/USB PHY as well as two PCIe-only PHYs.  The combo PHY port uses
> one PCIe lane, and the other two ports each have two lanes.  All PCIe
> ports operate at 5 GT/second.
> 
> The PCIe PHYs must be configured using a value that can only be
> determined using the combo PHY, operating in PCIe mode.  To allow
> that PHY to be used for USB, the needed calibration step is performed
> by the PHY driver automatically at probe time.  Once this step is done,
> the PHY can be used for either PCIe or USB.
> 
> The driver supports 256 MSIs, and initially does not support PCI INTx
> interrupts.  The hardware does not support MSI-X.
> 
> Version 6 of this series addresses a few comments from Christophe
> Jaillet, and improves a workaround that disables ASPM L1.  The two
> people who had reported errors on earlier versions of this code have
> confirmed their NVMe devices now work when configured with the default
> RISC-V kernel configuration.

I've tested this latest patchset on my Orange Pi RV2 board. This
patchset now works with the Intel 600p NVME SSD I had previously had
troublw with. Thanks!

Tested-by: Johannes Erdfelt <johannes@...felt.com>

JE