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Message-ID: <20251115042632.69708-5-akhilrajeev@nvidia.com>
Date: Sat, 15 Nov 2025 09:56:30 +0530
From: Akhil R <akhilrajeev@...dia.com>
To: <andi.shyti@...nel.org>, <digetx@...il.com>, <jonathanh@...dia.com>,
<linux-i2c@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-tegra@...r.kernel.org>, <thierry.reding@...il.com>,
<wsa+renesas@...g-engineering.com>, <wsa@...nel.org>
CC: <kkartik@...dia.com>, <akhilrajeev@...dia.com>, <ldewangan@...dia.com>,
<smangipudi@...dia.com>
Subject: [PATCH v12 4/6] i2c: tegra: Add HS mode support
Add support for HS (High Speed) mode transfers, which is supported by
Tegra194 onwards. Also adjust the bus frequency such that it uses the
fast plus mode when HS mode is not supported.
Signed-off-by: Akhil R <akhilrajeev@...dia.com>
Signed-off-by: Kartik Rajput <kkartik@...dia.com>
---
v10 -> v12:
* Update bus_freq_hz to max supported freq and updates to
accomodate the changes from Patch 2/6.
v10 -> v11:
* Update the if condition as per the comments received on:
https://lore.kernel.org/linux-tegra/20251110080502.865953-1-kkartik@nvidia.com/T/#t
v9 -> v10:
* Change switch block to an if-else block.
v5 -> v9:
* In the switch block, handle the case when hs mode is not
supported. Also update it to use Fast mode for master code
byte as per the I2C spec for HS mode.
v3 -> v5:
* Set has_hs_mode_support to false for unsupported SoCs.
v2 -> v3:
* Document tlow_hs_mode and thigh_hs_mode.
v1 -> v2:
* Document has_hs_mode_support.
* Add a check to set the frequency to fastmode+ if the device
does not support HS mode but the requested frequency is more
than fastmode+.
---
drivers/i2c/busses/i2c-tegra.c | 59 ++++++++++++++++++++++++++++++++--
1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 8a696c88882e..9ebeb6a2eaf5 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -91,6 +91,7 @@
#define I2C_HEADER_IE_ENABLE BIT(17)
#define I2C_HEADER_REPEAT_START BIT(16)
#define I2C_HEADER_CONTINUE_XFER BIT(15)
+#define I2C_HEADER_HS_MODE BIT(22)
#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
#define I2C_BUS_CLEAR_CNFG 0x084
@@ -200,6 +201,8 @@ enum msg_end_type {
* @thigh_fast_mode: High period of the clock in fast mode.
* @tlow_fastplus_mode: Low period of the clock in fast-plus mode.
* @thigh_fastplus_mode: High period of the clock in fast-plus mode.
+ * @tlow_hs_mode: Low period of the clock in HS mode.
+ * @thigh_hs_mode: High period of the clock in HS mode.
* @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
* in standard mode.
* @setup_hold_time_fast_mode: Setup and hold time for start and stop
@@ -210,6 +213,7 @@ enum msg_end_type {
* in HS mode.
* @has_interface_timing_reg: Has interface timing register to program the tuned
* timing settings.
+ * @has_hs_mode_support: Has support for high speed (HS) mode transfers.
*/
struct tegra_i2c_hw_feature {
bool has_continue_xfer_support;
@@ -232,11 +236,14 @@ struct tegra_i2c_hw_feature {
u32 thigh_fast_mode;
u32 tlow_fastplus_mode;
u32 thigh_fastplus_mode;
+ u32 tlow_hs_mode;
+ u32 thigh_hs_mode;
u32 setup_hold_time_std_mode;
u32 setup_hold_time_fast_mode;
u32 setup_hold_time_fastplus_mode;
u32 setup_hold_time_hs_mode;
bool has_interface_timing_reg;
+ bool has_hs_mode_support;
};
/**
@@ -646,6 +653,7 @@ static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev)
static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
{
u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
+ u32 max_bus_freq_hz;
struct i2c_timings *t = &i2c_dev->timings;
int err;
@@ -684,6 +692,14 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
if (IS_VI(i2c_dev))
tegra_i2c_vi_init(i2c_dev);
+ if (i2c_dev->hw->has_hs_mode_support)
+ max_bus_freq_hz = I2C_MAX_HIGH_SPEED_MODE_FREQ;
+ else
+ max_bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ;
+
+ if (WARN_ON(t->bus_freq_hz > max_bus_freq_hz))
+ t->bus_freq_hz = max_bus_freq_hz;
+
if (t->bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
tlow = i2c_dev->hw->tlow_std_mode;
thigh = i2c_dev->hw->thigh_std_mode;
@@ -694,11 +710,22 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
thigh = i2c_dev->hw->thigh_fast_mode;
tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode;
non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
- } else {
+ } else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
tlow = i2c_dev->hw->tlow_fastplus_mode;
thigh = i2c_dev->hw->thigh_fastplus_mode;
tsu_thd = i2c_dev->hw->setup_hold_time_fastplus_mode;
non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
+ } else {
+ /*
+ * When using HS mode, i.e. when the bus frequency is greater than fast plus mode,
+ * the non-hs timing registers will be used for sending the master code byte for
+ * transition to HS mode. Configure the non-hs timing registers for Fast Mode to
+ * send the master code byte at 400kHz.
+ */
+ tlow = i2c_dev->hw->tlow_fast_mode;
+ thigh = i2c_dev->hw->thigh_fast_mode;
+ tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode;
+ non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
}
/* make sure clock divisor programmed correctly */
@@ -720,6 +747,18 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
+ /* Write HS mode registers. These will get used only for HS mode*/
+ if (i2c_dev->hw->has_hs_mode_support) {
+ tlow = i2c_dev->hw->tlow_hs_mode;
+ thigh = i2c_dev->hw->thigh_hs_mode;
+ tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode;
+
+ val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) |
+ FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow);
+ i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0);
+ i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1);
+ }
+
clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
err = clk_set_rate(i2c_dev->div_clk,
@@ -1217,6 +1256,9 @@ static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
if (msg->flags & I2C_M_RD)
packet_header |= I2C_HEADER_READ;
+ if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
+ packet_header |= I2C_HEADER_HS_MODE;
+
if (i2c_dev->dma_mode && !i2c_dev->msg_read)
*dma_buf++ = packet_header;
else
@@ -1508,6 +1550,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
.setup_hold_time_fastplus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = false,
+ .has_hs_mode_support = false,
};
static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
@@ -1536,6 +1579,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
.setup_hold_time_fastplus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = false,
+ .has_hs_mode_support = false,
};
static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
@@ -1564,6 +1608,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
.setup_hold_time_fastplus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = false,
+ .has_hs_mode_support = false,
};
static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
@@ -1592,6 +1637,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
.setup_hold_time_fastplus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = true,
+ .has_hs_mode_support = false,
};
static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
@@ -1620,6 +1666,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
.setup_hold_time_fastplus_mode = 0,
.setup_hold_time_hs_mode = 0,
.has_interface_timing_reg = true,
+ .has_hs_mode_support = false,
};
static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
@@ -1648,6 +1695,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
.setup_hold_time_fastplus_mode = 0,
.setup_hold_time_hs_mode = 0,
.has_interface_timing_reg = true,
+ .has_hs_mode_support = false,
};
static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
@@ -1671,16 +1719,19 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
.thigh_fast_mode = 0x2,
.tlow_fastplus_mode = 0x2,
.thigh_fastplus_mode = 0x2,
+ .tlow_hs_mode = 0x8,
+ .thigh_hs_mode = 0x3,
.setup_hold_time_std_mode = 0x08080808,
.setup_hold_time_fast_mode = 0x02020202,
.setup_hold_time_fastplus_mode = 0x02020202,
.setup_hold_time_hs_mode = 0x090909,
.has_interface_timing_reg = true,
+ .has_hs_mode_support = true,
};
static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
.has_continue_xfer_support = true,
.has_per_pkt_xfer_complete_irq = true,
- .clk_divisor_hs_mode = 7,
+ .clk_divisor_hs_mode = 9,
.clk_divisor_std_mode = 0x7a,
.clk_divisor_fast_mode = 0x40,
.clk_divisor_fast_plus_mode = 0x14,
@@ -1698,10 +1749,14 @@ static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
.thigh_fast_mode = 0x2,
.tlow_fastplus_mode = 0x4,
.thigh_fastplus_mode = 0x4,
+ .tlow_hs_mode = 0x3,
+ .thigh_hs_mode = 0x2,
.setup_hold_time_std_mode = 0x08080808,
.setup_hold_time_fast_mode = 0x04010101,
.setup_hold_time_fastplus_mode = 0x04020202,
+ .setup_hold_time_hs_mode = 0x030303,
.has_interface_timing_reg = true,
+ .has_hs_mode_support = true,
};
static const struct of_device_id tegra_i2c_of_match[] = {
--
2.50.1
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