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Message-ID: <cover.1763197368.git.geraldogabriel@gmail.com>
Date: Sat, 15 Nov 2025 06:10:01 -0300
From: Geraldo Nascimento <geraldogabriel@...il.com>
To: linux-rockchip@...ts.infradead.org
Cc: Shawn Lin <shawn.lin@...k-chips.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kwilczynski@...nel.org>,
Manivannan Sadhasivam <mani@...nel.org>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Heiko Stuebner <heiko@...ech.de>, linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Johan Jonker <jbx6244@...il.com>,
Geraldo Nascimento <geraldogabriel@...il.com>,
Dragan Simic <dsimic@...jaro.org>
Subject: [PATCH 0/3] PCI: rockchip: 5.0 GT/s speed may be dangerous
In recent interactions with Shawn Lin from Rockchip it came to my
attention there's an unknown errata regarding 5.0 GT/s operational
speed of their PCIe core. According to Shawn there's grave danger
even if the odds are low. To contain any damage, let's cover the
remaining corner-cases where the default would lead to 5.0 GT/s
operation as well as add a comment to Root Complex driver core,
documenting this danger.
Geraldo Nascimento (3):
PCI: rockchip: warn of danger of 5.0 GT/s speeds
PCI: rockchip-host: comment danger of 5.0 GT/s speed
arm64: dts: rockchip: drop max-link-speed = <2> in helios64 PCIe
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 1 -
drivers/pci/controller/pcie-rockchip-host.c | 5 +++++
drivers/pci/controller/pcie-rockchip.c | 8 ++++++--
3 files changed, 11 insertions(+), 3 deletions(-)
--
2.49.0
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