linux-kernel - [PATCH v1] dt-bindings: cache: sifive,ccache0: add a pic64gx compatible

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Message-ID: <20251117-colt-carnival-8aab0a900816@spud>
Date: Mon, 17 Nov 2025 14:24:37 +0000
From: Conor Dooley <conor@...nel.org>
To: linux-kernel@...r.kernel.org
Cc: conor@...nel.org,
	Pierre-Henry Moussay <pierre-henry.moussay@...rochip.com>,
	Conor Dooley <conor.dooley@...rochip.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Paul Walmsley <pjw@...nel.org>,
	Samuel Holland <samuel.holland@...ive.com>,
	devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org
Subject: [PATCH v1] dt-bindings: cache: sifive,ccache0: add a pic64gx compatible

From: Pierre-Henry Moussay <pierre-henry.moussay@...rochip.com>

The pic64gx use the same IP than mpfs, therefore add compatibility with
mpfs as fallback.

Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@...rochip.com>
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
CC: Conor Dooley <conor@...nel.org>
CC: Rob Herring <robh@...nel.org>
CC: Krzysztof Kozlowski <krzk+dt@...nel.org>
CC: Paul Walmsley <pjw@...nel.org>
CC: Samuel Holland <samuel.holland@...ive.com>
CC: devicetree@...r.kernel.org
CC: linux-riscv@...ts.infradead.org
CC: linux-kernel@...r.kernel.org
 Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 579bacb66f34..c0e5ebb1fa4c 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -48,6 +48,11 @@ properties:
           - const: microchip,mpfs-ccache
           - const: sifive,fu540-c000-ccache
           - const: cache
+      - items:
+          - const: microchip,pic64gx-ccache
+          - const: microchip,mpfs-ccache
+          - const: sifive,fu540-c000-ccache
+          - const: cache
 
   cache-block-size:
     const: 64
-- 
2.51.0