[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <176339133088.9268.13766811346004998135.b4-ty@kernel.org>
Date: Mon, 17 Nov 2025 20:25:30 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
To: dlan@...too.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
vkoul@...nel.org, kishon@...nel.org, bhelgaas@...gle.com,
lpieralisi@...nel.org, kwilczynski@...nel.org,
Alex Elder <elder@...cstar.com>
Cc: ziyao@...root.org, aurelien@...el32.net, johannes@...felt.com,
mayank.rana@....qualcomm.com, qiang.yu@....qualcomm.com,
shradha.t@...sung.com, inochiama@...il.com, pjw@...nel.org,
palmer@...belt.com, aou@...s.berkeley.edu, alex@...ti.fr,
p.zabel@...gutronix.de, christian.bruel@...s.st.com,
thippeswamy.havalige@....com, krishna.chundru@....qualcomm.com,
guodong@...cstar.com, devicetree@...r.kernel.org,
linux-pci@...r.kernel.org, linux-phy@...ts.infradead.org,
spacemit@...ts.linux.dev, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: (subset) [PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and
host controller
On Thu, 13 Nov 2025 15:45:32 -0600, Alex Elder wrote:
> This series introduces a PHY driver and a PCIe driver to support PCIe
> on the SpacemiT K1 SoC. The PCIe implementation is derived from a
> Synopsys DesignWare PCIe IP. The PHY driver supports one combination
> PCIe/USB PHY as well as two PCIe-only PHYs. The combo PHY port uses
> one PCIe lane, and the other two ports each have two lanes. All PCIe
> ports operate at 5 GT/second.
>
> [...]
Applied, thanks!
[3/7] dt-bindings: pci: spacemit: Introduce PCIe host controller
commit: a812b09a6b599ea80ec1065a9a635724a235843d
[5/7] PCI: spacemit: Add SpacemiT PCIe host driver
commit: ff64e078e45faee50cc6ca7900a3520e8ff1c79e
Best regards,
--
Manivannan Sadhasivam <mani@...nel.org>
Powered by blists - more mailing lists