Message-ID: <4afa0534-5458-ac0c-6c92-38ed52aea00b@manjaro.org>
Date: Mon, 17 Nov 2025 16:59:05 +0100
From: "Dragan Simic" <dsimic@...jaro.org>
To: "Geraldo Nascimento" <geraldogabriel@...il.com>
Cc: "Shawn Lin" <shawn.lin@...k-chips.com>, "Lorenzo Pieralisi" <lpieralisi@...nel.org>, Krzysztof Wilczyński <kwilczynski@...nel.org>, "Manivannan Sadhasivam" <mani@...nel.org>, "Rob Herring" <robh@...nel.org>, "Bjorn Helgaas" <bhelgaas@...gle.com>, "Heiko Stuebner" <heiko@...ech.de>, linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, "Krzysztof Kozlowski" <krzk+dt@...nel.org>, "Conor Dooley" <conor+dt@...nel.org>, "Johan Jonker" <jbx6244@...il.com>, linux-rockchip@...ts.infradead.org
Subject: Re: [PATCH 0/3] PCI: rockchip: 5.0 GT/s speed may be dangerous

Hello Geraldo,

On Monday, November 17, 2025 08:02 CET, Geraldo Nascimento <geraldogabriel@...il.com> wrote:
> On Mon, Nov 17, 2025 at 04:57:11AM +0100, Dragan Simic wrote:
> > On Monday, November 17, 2025 04:42 CET, Shawn Lin <shawn.lin@...k-chips.com> wrote:
> > > 在 2025/11/15 星期六 17:10, Geraldo Nascimento 写道:
> > > > In recent interactions with Shawn Lin from Rockchip it came to my
> > > > attention there's an unknown errata regarding 5.0 GT/s operational
> > > > speed of their PCIe core. According to Shawn there's grave danger
> > > > even if the odds are low. To contain any damage, let's cover the
> > > > remaining corner-cases where the default would lead to 5.0 GT/s
> > > > operation as well as add a comment to Root Complex driver core,
> > > > documenting this danger.
> > > 
> > > I'm not sure just adding a warn would be a good choice. Could we totally
> > > force to use gen1 and add a warn if trying to use Gen2.
> > 
> > I think that forcing 2.5 GT/s with an appropriate warning message
> > is a good idea.  That would be like some quirk that gets applied
> > automatically, to prevent data corruption, while warning people
> > who attempt to "overclock" the PCIe interface.
> 
> Alright, I'll send v2 with this suggestion in mind. So that driving the
> core at 5.0 GT/s will require patching and compiling own kernel.
> 
> > > Meanwhile amend the commit message to add a reference
> > > of RK3399 official datesheet[1] which says PCIe on RK3399 should only
> > > support 2.5GT/s?
> > > 
> > > [1]https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> > 
> 
> Shawn, URLs have the bad habit of changing or simply disappearing, so I
> don't think it's a good idea to put URL in the commit message.

Ah, it's actually perfectly fine, there's always Wayback Machibe
to rescue references/URLs that may disappear over time.  Wikipedia
relies heavily on exactly that mechanism, for example.

[2] https://web.archive.org/

> Also, the datasheet just mentions that RK3399 supports only 2.5 GT/s,
> it does not mention possible damage from driving the core at 5.0 GT/s.

True, but having an additional reference doesn't hurt, especially
because the revision history mentions, albeit vaguely, an update
to the PCIe specification in version 1.1.of the datasheet.  Though,
if we had the version 1.0 publicly available for comparison, that
would've been much better. :)

> > Also, rewording the patch summary as follows below may be good,
> > because that would provide more details:
> > 
> >   PCI: rockchip: Warn about Gen2 5.0 GT/s on RK3399 being unsafe
> > 
> > Or, if we'll go with the automatic downgrading, like this:
> > 
> >   PCI: rockchip: Limit RK3399 to Gen1 2.5 GT/s to prevent breakage
> 
> Dragan, these are good ones, thanks. Though I think I'll omit Gen1/Gen2
> wording since I know how much Bjorn dislikes those terms.

I'm glad that you like those, and I also thought about not including
the GenX parts, because they're basically a bit redundant. :)

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