linux-kernel - Re: [PATCH v5 6/8] PCI: Add FMT, TYPE and CPL status definition for TLP header

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Message-ID: <20251117172859.GA2466937@bhelgaas>
Date: Mon, 17 Nov 2025 11:28:59 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Jacky Chou <jacky_chou@...eedtech.com>
Cc: Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Joel Stanley <joel@....id.au>,
	Andrew Jeffery <andrew@...econstruct.com.au>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof Wilczyński <kwilczynski@...nel.org>,
	Manivannan Sadhasivam <mani@...nel.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	linux-aspeed@...ts.ozlabs.org, linux-pci@...r.kernel.org,
	linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Andrew Jeffery <andrew@...id.au>, openbmc@...ts.ozlabs.org,
	linux-gpio@...r.kernel.org
Subject: Re: [PATCH v5 6/8] PCI: Add FMT, TYPE and CPL status definition for
 TLP header

On Mon, Nov 17, 2025 at 08:37:53PM +0800, Jacky Chou wrote:
> According to PCIe specification, add FMT, TYPE and CPL status
> definition for TLP header.
> 
> Signed-off-by: Jacky Chou <jacky_chou@...eedtech.com>

Acked-by: Bjorn Helgaas <bhelgaas@...gle.com>

OK by me, but it'd be nice to move up a few lines so this is with the
other TLP-related items and the unrelated PCI_BUS_BRIDGE_*_WINDOW
values aren't in the middle.

Might even consider moving these to be just above the Message Routing
constants so things are generally in the order they appear in the
spec.

> ---
>  drivers/pci/pci.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 36f8c0985430..3a075f77cf4a 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -88,6 +88,21 @@ struct pcie_tlp_log;
>  #define PCI_BUS_BRIDGE_MEM_WINDOW	1
>  #define PCI_BUS_BRIDGE_PREF_MEM_WINDOW	2
>  
> +/* Format of TLP; PCIe r7.0, sec 2.2.1 */
> +#define PCIE_TLP_FMT_3DW_NO_DATA	0x00 /* 3DW header, no data */
> +#define PCIE_TLP_FMT_4DW_NO_DATA	0x01 /* 4DW header, no data */
> +#define PCIE_TLP_FMT_3DW_DATA		0x02 /* 3DW header, with data */
> +#define PCIE_TLP_FMT_4DW_DATA		0x03 /* 4DW header, with data */
> +
> +/* Type of TLP; PCIe r7.0, sec 2.2.1 */
> +#define PCIE_TLP_TYPE_CFG0_RD		0x04 /* Config Type 0 Read Request */
> +#define PCIE_TLP_TYPE_CFG0_WR		0x04 /* Config Type 0 Write Request */
> +#define PCIE_TLP_TYPE_CFG1_RD		0x05 /* Config Type 1 Read Request */
> +#define PCIE_TLP_TYPE_CFG1_WR		0x05 /* Config Type 1 Write Request */
> +
> +/* Cpl. status of Complete; PCIe r7.0, sec 2.2.9.1 */
> +#define PCIE_CPL_STS_SUCCESS		0x00 /* Successful Completion */
> +
>  extern const unsigned char pcie_link_speed[];
>  extern bool pci_early_dump;
>  
> 
> -- 
> 2.34.1
>