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Message-ID: <20251117180848.GH10864@nvidia.com>
Date: Mon, 17 Nov 2025 14:08:48 -0400
From: Jason Gunthorpe <jgg@...dia.com>
To: "Suthikulpanit, Suravee" <suravee.suthikulpanit@....com>
Cc: Vasant Hegde <vasant.hegde@....com>, nicolinc@...dia.com,
linux-kernel@...r.kernel.org, robin.murphy@....com, will@...nel.org,
joro@...tes.org, kevin.tian@...el.com, jsnitsel@...hat.com,
iommu@...ts.linux.dev, santosh.shukla@....com,
sairaj.arunkodilkar@....com, jon.grimm@....com,
prashanthpra@...gle.com, wvw@...gle.com, wnliu@...gle.com,
gptran@...gle.com, kpsingh@...gle.com, joao.m.martins@...cle.com,
alejandro.j.jimenez@...cle.com
Subject: Re: [PATCH v4 15/16] iommu/amd: Refactor logic to program the host
page table in DTE
On Thu, Nov 13, 2025 at 01:40:47AM +0700, Suthikulpanit, Suravee wrote:
>
>
> On 11/9/2025 6:03 AM, Jason Gunthorpe wrote:
> > On Sat, Nov 08, 2025 at 10:56:38PM +0530, Vasant Hegde wrote:
> > > On 10/23/2025 6:38 PM, Jason Gunthorpe wrote:
> > > > On Tue, Oct 21, 2025 at 01:43:23AM +0000, Suravee Suthikulpanit wrote:
> > > >
> > > > (though how does IDENTITY on a device with a PASID installed work?)
> > >
> > > Probably set_dte_identity() should call set_dte_gcr3_table () and update
> > > relevant fields.
>
> Actually, PASID would not work with IDENTITY since it has no page table
> (i.e. iommu=pt means DTE[Mode]=0 and does not have host table pointer).
> PASID only work with GCR3 table.
>
> Therefore, it does not make sense for set_dte_identity() to call
> set_dte_gcr3_table(). Each one should be stand alone.
OK, so the HW cannot do this?
On SMMUv3 there are bits in the "DTE" (S1DSS) that control how
no-PASID, ie PASID 0 transactions are handled which allow it to be set
to indentity. Intel can do the same.
IMHO this is a HW gap that AMD probably should fix.
In the mean time the driver should be blocking this unsupported
combination, I don't remember seeing that code? It will make it more
difficult to use SVA on AMD platforms, but not much that can be done
about that :\
Jason
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