linux-kernel - Re: [PATCH v3 1/2] iommupt: Do not set C-bit on MMIO backed PTEs

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Message-ID: <20251117191526.GI10864@nvidia.com>
Date: Mon, 17 Nov 2025 15:15:26 -0400
From: Jason Gunthorpe <jgg@...dia.com>
To: Wei Wang <wei.w.wang@...mail.com>
Cc: alex@...zbot.org, thomas.lendacky@....com, vasant.hegde@....com,
	suravee.suthikulpanit@....com, joro@...tes.org, aik@....com,
	kevin.tian@...el.com, linux-kernel@...r.kernel.org,
	iommu@...ts.linux.dev
Subject: Re: [PATCH v3 1/2] iommupt: Do not set C-bit on MMIO backed PTEs

On Thu, Nov 13, 2025 at 11:54:06PM +0800, Wei Wang wrote:
> AMD Secure Memory Encryption (SME) marks individual memory pages as
> encrypted by setting the C-bit in page table entries. According to the
> AMD APM,any pages corresponding to MMIO addresses must be configured
> with the C-bit clear.
> 
> The current *_iommu_set_prot() implementation sets the C-bit on all PTEs
> in the IOMMU page tables. This is incorrect for PTEs backed by MMIO, and
> can break PCIe peer-to-peer communication when IOVA is used. Fix this by
> avoiding the C-bit for MMIO-backed mappings.
> 
> For amdv2 IOMMU page tables, there is a usage scenario for GVA->GPA
> mappings, and for the trusted MMIO in the TEE-IO case, the C-bit will need
> to be added to GPA. However, SNP guests do not yet support vIOMMU, and the
> trusted MMIO support is not ready in upstream. Adding the C-bit for trusted
> MMIO can be considered once those features land.
> 
> Fixes: 879ced2bab1b ("iommupt: Add the AMD IOMMU v1 page table format")
> Fixes: aef5de756ea8 ("iommupt: Add the x86 64 bit page table format")
> Suggested-by: Jason Gunthorpe <jgg@...dia.com>
> Signed-off-by: Wei Wang <wei.w.wang@...mail.com>
> ---
>  drivers/iommu/generic_pt/fmt/amdv1.h  | 3 ++-
>  drivers/iommu/generic_pt/fmt/x86_64.h | 3 ++-
>  2 files changed, 4 insertions(+), 2 deletions(-)

Reviewed-by: Jason Gunthorpe <jgg@...dia.com>

Jason