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Message-ID: <cdbfe200-314b-4185-bb58-d528ed317610@oss.qualcomm.com>
Date: Mon, 17 Nov 2025 13:28:46 +0530
From: Taniya Das <taniya.das@....qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>, jingyi.wang@....qualcomm.com,
aiqun.yu@....qualcomm.com, Ajit Pandey <ajit.pandey@....qualcomm.com>,
Imran Shaik <imran.shaik@....qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@....qualcomm.com>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 4/6] clk: qcom: rpmh: Add support for Kaanapali rpmh
clocks
On 11/14/2025 4:38 PM, Dmitry Baryshkov wrote:
> On Fri, Nov 14, 2025 at 02:13:49PM +0530, Taniya Das wrote:
>>
>>
>> On 11/11/2025 4:16 PM, Dmitry Baryshkov wrote:
>>> On Thu, Oct 30, 2025 at 04:39:07PM +0530, Taniya Das wrote:
>>>> Add the RPMH clocks present in Kaanapali SoC.
>>>>
>>>> Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
>>>> Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
>>>> ---
>>>> drivers/clk/qcom/clk-rpmh.c | 42 ++++++++++++++++++++++++++++++++++++++++++
>>>> 1 file changed, 42 insertions(+)
>>>>
>>>> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
>>>> index 1a98b3a0c528c24b600326e6b951b2edb6dcadd7..fd0fe312a7f2830a27e6effc0c0bd905d9d5ebed 100644
>>>> --- a/drivers/clk/qcom/clk-rpmh.c
>>>> +++ b/drivers/clk/qcom/clk-rpmh.c
>>>> @@ -395,6 +395,19 @@ DEFINE_CLK_RPMH_VRM(clk4, _a, "C4A_E0", 1);
>>>> DEFINE_CLK_RPMH_VRM(clk5, _a, "C5A_E0", 1);
>>>> DEFINE_CLK_RPMH_VRM(clk8, _a, "C8A_E0", 1);
>>>>
>>>> +DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2_e0, "C6A_E0", 2);
>>>> +DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2_e0, "C7A_E0", 2);
>>>> +DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2_e0, "C8A_E0", 2);
>>>> +
>>>> +DEFINE_CLK_RPMH_VRM(rf_clk1, _a_e0, "C1A_E0", 1);
>>>> +DEFINE_CLK_RPMH_VRM(rf_clk2, _a_e0, "C2A_E0", 1);
>>>
>>> What is the difference between these clocks and clk[3458] defined few
>>> lines above? Why are they named differently? If the other name is
>>> incorrect, please fix it.
>>>
>>
>> Dmitry, my intention was to make a clear distinction between the ‘rf’
>> clocks and the ‘ln’ clocks. Since there could be overlap in the
>> numbering, I added prefixes for clarity. I should have applied the same
>> approach to clk[3458] as well. I will add the fix-up for the same.
>
> Why do we need to distinguish between them here? The resources in CMD-DB
> don't have such a difference. You'll select whether the clock is RF or
> LN when describing the platform data.
>
It is more for readibility and maintain a direct mapping with the PMIC
clock grid. This way we can immediately identify the clock type without
cross-referencing desc as the clock mapping here would indicate the type
of clock. Yes, the CMD-DB name does not reflect anything with the names
here. Please do let me know your suggestion.
>>
>>>> +
>>>> +DEFINE_CLK_RPMH_VRM(rf_clk3, _a2_e0, "C3A_E0", 2);
>>>> +DEFINE_CLK_RPMH_VRM(rf_clk4, _a2_e0, "C4A_E0", 2);
>>>> +DEFINE_CLK_RPMH_VRM(rf_clk5, _a2_e0, "C5A_E0", 2);
>>>> +
>>>> +DEFINE_CLK_RPMH_VRM(div_clk1, _a4_e0, "C11A_E0", 4);
>>>> +
>>>> DEFINE_CLK_RPMH_BCM(ce, "CE0");
>>>> DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
>>>> DEFINE_CLK_RPMH_BCM(ipa, "IP0");
>>>> @@ -901,6 +914,34 @@ static const struct clk_rpmh_desc clk_rpmh_glymur = {
>>>> .num_clks = ARRAY_SIZE(glymur_rpmh_clocks),
>>>> };
>>>>
>>>> +static struct clk_hw *kaanapali_rpmh_clocks[] = {
>>>> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
>>>> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
>>>> + [RPMH_DIV_CLK1] = &clk_rpmh_div_clk1_a4_e0.hw,
>>>> + [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2_e0.hw,
>>>> + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_e0_ao.hw,
>>>> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2_e0.hw,
>>>> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_e0_ao.hw,
>>>> + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2_e0.hw,
>>>> + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_e0_ao.hw,
>>>> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a_e0.hw,
>>>> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_e0_ao.hw,
>>>> + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a_e0.hw,
>>>> + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_e0_ao.hw,
>>>> + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a2_e0.hw,
>>>> + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a2_e0_ao.hw,
>>>> + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a2_e0.hw,
>>>> + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a2_e0_ao.hw,
>>>> + [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a2_e0.hw,
>>>> + [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a2_e0_ao.hw,
>>>> + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
>>>> +};
>>>> +
>>>> +static const struct clk_rpmh_desc clk_rpmh_kaanapali = {
>>>> + .clks = kaanapali_rpmh_clocks,
>>>> + .num_clks = ARRAY_SIZE(kaanapali_rpmh_clocks),
>>>> +};
>>>> +
>>>> static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
>>>> void *data)
>>>> {
>>>> @@ -991,6 +1032,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
>>>>
>>>> static const struct of_device_id clk_rpmh_match_table[] = {
>>>> { .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
>>>> + { .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
>>>> { .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos},
>>>> { .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615},
>>>> { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},
>>>>
>>>> --
>>>> 2.34.1
>>>>
>>>
>>
>> --
>> Thanks,
>> Taniya Das
>>
>
--
Thanks,
Taniya Das
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