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Message-ID: <20251117085134.289371-3-sh86.bae@samsung.com>
Date: Mon, 17 Nov 2025 17:51:34 +0900
From: Sanghoon Bae <sh86.bae@...sung.com>
To: robh@...nel.org, krzk@...nel.org, conor+dt@...nel.org, vkoul@...nel.org,
	alim.akhtar@...sung.com, kishon@...nel.org
Cc: krzk+dt@...nel.org, linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
	sowon.na@...sung.com, Sanghoon Bae <sh86.bae@...sung.com>
Subject: [PATCH 0/1] Add ExynosAutov920 hsi0 support to exynos-sysreg

The ExynosAutov920 SoC includes a PCIe IP and a hsi0 register block that
is mapped in the exynos-sysreg.

To manage PCIe PHY power, configure the PCIe PLL, and set the device direction,
the hsi0 registers need to be defined in exynos-sysreg.

This patch must be applied before the ExynosAutov920 PCIe PHY is enabled.

Sanghoon Bae (1):
  dt-bindings: soc: samsung: exynos-sysreg: add hsi0 for ExynosAutov920

 .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml   | 1 +
 1 file changed, 1 insertion(+)

-- 
2.45.2


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