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Message-ID: <20251117-upstream_pcie_rc-v5-0-b4a198576acf@aspeedtech.com>
Date: Mon, 17 Nov 2025 20:37:47 +0800
From: Jacky Chou <jacky_chou@...eedtech.com>
To: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Joel Stanley <joel@....id.au>, "Andrew
Jeffery" <andrew@...econstruct.com.au>, Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kwilczynski@...nel.org>, "Manivannan
Sadhasivam" <mani@...nel.org>, Linus Walleij <linus.walleij@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>
CC: <linux-aspeed@...ts.ozlabs.org>, <linux-pci@...r.kernel.org>,
<linux-phy@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
Andrew Jeffery <andrew@...id.au>, <openbmc@...ts.ozlabs.org>,
<linux-gpio@...r.kernel.org>, Jacky Chou <jacky_chou@...eedtech.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH v5 0/8] Add ASPEED PCIe Root Complex support
This patch series adds support for the ASPEED PCIe Root Complex,
including device tree bindings, pinctrl support, and the PCIe host controller
driver. The patches introduce the necessary device tree nodes, pinmux groups,
and driver implementation to enable PCIe functionality on ASPEED platforms.
Currently, the ASPEED PCIe Root Complex only supports a single port.
Summary of changes:
- Add device tree binding documents for ASPEED PCIe PHY, PCIe Config, and PCIe RC
- Update MAINTAINERS for new bindings and driver
- Add PCIe RC node and PERST control pin to aspeed-g6 device tree
- Implement ASPEED PCIe PHY driver
- Implement ASPEED PCIe Root Complex host controller driver
This series has been tested on AST2600/AST2700 platforms and enables PCIe device
enumeration and operation.
Signed-off-by: Jacky Chou <jacky_chou@...eedtech.com>
---
Changes in v5:
- Remove legacy-interrupt-controller and the INTx points to pcie node itself.
- Correct bar mapping description and implementation to PCIe address
configuration in pcie-aspeed.c driver.
- Link to v4: https://lore.kernel.org/r/20251027095825.181161-1-jacky_chou@aspeedtech.com/
Changes in v4:
- Remove aspeed,ast2700-pcie-cfg.yaml
- Add more descriptions for AST2600 PCIe RC in aspeed,ast2600-pcie.yaml
- Change interrupt-controller to legacy-interrupt-controller in yaml
and dtsi
- Remove msi-parent property in yaml and dtsi
- Modify the bus range to starting from 0x00 in aspeed-g6.dtsi
- Fixed the typo on MODULE_DEVICE_TABLE() in phy-aspeed-pcie.c
- Add PCIE_CPL_STS_SUCCESS definition in pci/pci.h
- Add prefix ASPEED_ for register definition in RC driver
- Add a flag to indicate clear msi status twice for AST2700 workaround
- Remove getting domain number
- Remove scanning AST2600 HOST bridge on device number 0
- Remove all codes about CONFIG_PCI_MSI
- Get root but number from resouce list by IORESOURCE_BUS
- Change module_platform_driver to builtin_platform_driver
- Link to v3: https://lore.kernel.org/r/20250901055922.1553550-1-jacky_chou@aspeedtech.com/
Changes in v3:
- Add ASPEED PCIe PHY driver
- Remove the aspeed,pciecfg property from AST2600 RC node, merged into RC node
- Update the binding doc for aspeed,ast2700-pcie-cfg to reflect the changes
- Update the binding doc for aspeed,ast2600-pcie to reflect the changes
- Update the binding doc for aspeed,ast2600-pinctrl to reflect the changes
- Update the device tree source to reflect the changes
- Adjusted the use of mutex in RC drivers to use GRAND
- Updated from reviewer comments
- Link to v2: https://lore.kernel.org/r/20250715034320.2553837-1-jacky_chou@aspeedtech.com/
Changes in v2:
- Moved ASPEED PCIe PHY yaml binding to `soc/aspeed` directory and
changed it as syscon
- Added `MAINTAINERS` entry for the new PCIe RC driver
- Updated device tree bindings to reflect the new structure
- Refactored configuration read and write functions to main bus and
child bus ops
- Refactored initialization to implement multiple ports support
- Added PCIe FMT and TYPE definitions for TLP header in
`include/uapi/linux/pci_regs.h`
- Updated from reviewer comments
- Link to v1: https://lore.kernel.org/r/20250613033001.3153637-1-jacky_chou@aspeedtech.com/
---
Jacky Chou (8):
dt-bindings: phy: aspeed: Add ASPEED PCIe PHY
dt-bindings: PCI: Add ASPEED PCIe RC support
dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group
ARM: dts: aspeed-g6: Add PCIe RC and PCIe PHY node
PHY: aspeed: Add ASPEED PCIe PHY driver
PCI: Add FMT, TYPE and CPL status definition for TLP header
PCI: aspeed: Add ASPEED PCIe RC driver
MAINTAINERS: Add ASPEED PCIe RC driver
.../bindings/pci/aspeed,ast2600-pcie.yaml | 149 +++
.../bindings/phy/aspeed,ast2600-pcie-phy.yaml | 42 +
.../bindings/pinctrl/aspeed,ast2600-pinctrl.yaml | 2 +
MAINTAINERS | 12 +
arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 5 +
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 50 +
drivers/pci/controller/Kconfig | 16 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-aspeed.c | 1117 ++++++++++++++++++++
drivers/pci/pci.h | 15 +
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/aspeed/Kconfig | 15 +
drivers/phy/aspeed/Makefile | 2 +
drivers/phy/aspeed/phy-aspeed-pcie.c | 209 ++++
15 files changed, 1637 insertions(+)
---
base-commit: 6a23ae0a96a600d1d12557add110e0bb6e32730c
change-id: 20251103-upstream_pcie_rc-8445759db813
Best regards,
--
Jacky Chou <jacky_chou@...eedtech.com>
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