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Message-ID: <mafs0v7j74iz0.fsf@kernel.org>
Date: Tue, 18 Nov 2025 13:34:59 +0100
From: Pratyush Yadav <pratyush@...nel.org>
To: Jakub Czapiga <czapiga@...gle.com>
Cc: Tudor Ambarus <tudor.ambarus@...aro.org>, Pratyush Yadav
<pratyush@...nel.org>, Michael Walle <mwalle@...nel.org>, Miquel Raynal
<miquel.raynal@...tlin.com>, Richard Weinberger <richard@....at>,
Vignesh Raghavendra <vigneshr@...com>, linux-mtd@...ts.infradead.org,
linux-kernel@...r.kernel.org, Konrad Adamczyk <konrada@...gle.com>,
Adeel Arshad <adeel.arshad@...el.com>, Mika Westerberg
<mika.westerberg@...ux.intel.com>, Kornel Duleba <korneld@...gle.com>
Subject: Re: [PATCH v2] mtd: spi-nor: core: Check read CR support
On Fri, Sep 19 2025, Jakub Czapiga wrote:
> Some SPI controllers like Intel's one on the PCI bus do not support
> opcode 35h. This opcode is used to read the Configuration Register on
> SPI-NOR chips that have 16-bit Status Register configured regardless
> of the controller support for it. Adding a check call in the setup step
> allows disabling use of the 35h opcode and falling back to the manual
> Status Registers management.
>
> Before:
> openat(AT_FDCWD, "/dev/mtd0", O_RDWR) = 4
> ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = -1
> EOPNOTSUPP
>
> After:
> openat(AT_FDCWD, "/dev/mtd0", O_RDWR) = 4
> ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = 0
> ioctl(4, MIXER_WRITE(5) or MEMLOCK, {start=0x1800000, length=0x800000}) = 0
>
> Suggested-by: Adeel Arshad <adeel.arshad@...el.com>
> Signed-off-by: Jakub Czapiga <czapiga@...gle.com>
Reviewed-by: Pratyush Yadav <pratyush@...nel.org>
Applied to spi-nor/next. Thanks!
BTW, b4 complains that DKIM fails on your email. Please check.
[...]
--
Regards,
Pratyush Yadav
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