linux-kernel - [PATCH 2/2] arm64: dts: renesas: r9a09g047e57-smarc: Add overlay for P3T1085UK-ARD

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Message-ID: <0babc991d3b2163200bc083ef80563931d4b639a.1763475830.git.tommaso.merciai.xr@bp.renesas.com>
Date: Tue, 18 Nov 2025 15:26:39 +0100
From: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
To: tomm.merciai@...il.com
Cc: linux-renesas-soc@...r.kernel.org,
	biju.das.jz@...renesas.com,
	Tommaso Merciai <tommaso.merciai.xr@...renesas.com>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH 2/2] arm64: dts: renesas: r9a09g047e57-smarc: Add overlay for P3T1085UK-ARD

Add a device tree overlay to enable support for the NXP P3T1085UK-ARD
board when connected to the RZ/G3E SMARC SoM via the RZ SMARC BREAKOUT
board.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  3 +
 .../r9a09g047e57-smarc-p3t1085uk-ard.dtso     | 83 +++++++++++++++++++
 2 files changed, 86 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc-p3t1085uk-ard.dtso

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 1fab1b50f20e..9e5b22343071 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -185,6 +185,9 @@ dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
 dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-cru-csi-ov5645.dtbo
 r9a09g047e57-smarc-cru-csi-ov5645-dtbs := r9a09g047e57-smarc.dtb r9a09g047e57-smarc-cru-csi-ov5645.dtbo
 dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-cru-csi-ov5645.dtb
+dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-p3t1085uk-ard.dtbo
+r9a09g047e57-smarc-p3t1085uk-ard-dtbs := r9a09g047e57-smarc.dtb r9a09g047e57-smarc-p3t1085uk-ard.dtbo
+dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-p3t1085uk-ard.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk.dtb
 dtb-$(CONFIG_ARCH_R9A09G056) += rzv2-evk-cn15-emmc.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc-p3t1085uk-ard.dtso b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc-p3t1085uk-ard.dtso
new file mode 100644
index 000000000000..fcbdccc942a8
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc-p3t1085uk-ard.dtso
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree overlay for the NXP P3T1085UK-ARD board connected
+ * to the R9A09G047E57 SMARC SoM board via the RZ SMARC BREAKOUT board.
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ *
+ * [Connections]
+ *
+ * RZ SMARC Carrier II (CN1)  →  RZ SMARC BREAKOUT board
+ *
+ * RZ SMARC Carrier II (PMOD1_6)  →  P3T1085UK-ARD (J9)
+ * +--------------------------------------------------------+
+ * |    PWR_PMOD1  (pin 6)    →    (pin 9)   +3V3           |
+ * |    GND        (pin 5)    →    (pin 7)   GND            |
+ * +--------------------------------------------------------+
+ *
+ * RZ SMARC BREAKOUT board (CN1)  →  P3T1085UK-ARD (J13)
+ * +--------------------------------------------------------+
+ * |    GND      (pin 2)    →    (pin 4)   GND              |
+ * |    I3C_SCL  (pin 3)    →    (pin 1)   SCL_I3C          |
+ * |    I3C_SDA  (pin 4)    →    (pin 2)   SDA_I3C          |
+ * +--------------------------------------------------------+
+ *
+ * The following jumpers setup is required on the P3T1085UK-ARD board:
+ * - JP1: 1-2
+ * - JP2: 1-2
+ * - JP3: 1-2
+ *
+ * The following SW1(1,2) switch setup is required on the RZ SMARC BREAKOUT
+ * board:
+ * - SW1(1): 1
+ * - SW1(2): 1
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/i3c/i3c.h>
+#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
+
+/*
+ * #define I3C_BUS_MODE_PURE 1 (for I3C bus mode pure - default)
+ * #define I3C_BUS_MODE_PURE 0 (for I3C bus mode mixed-fast)
+ */
+#define I3C_BUS_MODE_PURE	1
+
+#if I3C_BUS_MODE_PURE
+&i3c {
+	i2c-scl-hz = <400000>;
+	i3c-scl-hz = <12500000>;
+	status = "okay";
+};
+#else /* I3C_BUS_MODE_MIXED_FAST */
+&i3c {
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	i2c-scl-hz = <400000>;
+	i3c-scl-hz = <12500000>;
+
+	eeprom@1a {
+		compatible = "atmel,24c02";
+		reg = <0x1a 0 (I2C_FM | I2C_FILTER)>;
+	};
+
+	/* U2 */
+	temperature-sensor@48 {
+		compatible = "nxp,p3t1085";
+		reg = <0x48 0 (I2C_FM | I2C_FILTER)>;
+	};
+
+	/* U1 NOT MOUNTED as default */
+	temp-sense@4c {
+		status = "disabled";
+		compatible = "national,lm75";
+		reg = <0x4c 0 (I2C_FM | I2C_FILTER)>;
+	};
+};
+#endif
-- 
2.43.0