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Message-ID: <20251118161936.1085477-14-antonio.borneo@foss.st.com>
Date: Tue, 18 Nov 2025 17:19:34 +0100
From: Antonio Borneo <antonio.borneo@...s.st.com>
To: Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue
<alexandre.torgue@...s.st.com>,
<linux-gpio@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
CC: Antonio Borneo <antonio.borneo@...s.st.com>,
Clément Le Goffic <legoffic.clement@...il.com>,
"Amelie
Delaunay" <amelie.delaunay@...s.st.com>,
Pascal Paillet
<p.paillet@...s.st.com>
Subject: [PATCH v2 13/15] arm64: dts: st: add pinctrl nodes on stm32mp21
Update the device-tree stm32mp211.dtsi to add the nodes for pinctrl.
Signed-off-by: Antonio Borneo <antonio.borneo@...s.st.com>
---
arch/arm64/boot/dts/st/stm32mp211.dtsi | 142 +++++++++++++++++++++++++
1 file changed, 142 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi
index 4bdf4b3a39829..fd561a85027c3 100644
--- a/arch/arm64/boot/dts/st/stm32mp211.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@...s.st.com> for STMicroelectronics.
*/
+#include <dt-bindings/clock/st,stm32mp21-rcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -205,6 +206,124 @@ syscfg: syscon@...30000 {
reg = <0x44230000 0x0 0x10000>;
};
+ pinctrl: pinctrl@...40000 {
+ bootph-all;
+ compatible = "st,stm32mp215-pinctrl";
+ ranges = <0 0x44240000 0x80400>;
+ interrupt-parent = <&exti1>;
+ st,syscfg = <&exti1 0x60 0xff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpioa: gpio@...40000 {
+ bootph-all;
+ reg = <0x0 0x400>;
+ clocks = <&scmi_clk CK_SCMI_GPIOA>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,bank-name = "GPIOA";
+ status = "disabled";
+ };
+
+ gpiob: gpio@...50000 {
+ bootph-all;
+ reg = <0x10000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_GPIOB>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,bank-name = "GPIOB";
+ status = "disabled";
+ };
+
+ gpioc: gpio@...60000 {
+ bootph-all;
+ reg = <0x20000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_GPIOC>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,bank-name = "GPIOC";
+ status = "disabled";
+ };
+
+ gpiod: gpio@...70000 {
+ bootph-all;
+ reg = <0x30000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_GPIOD>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,bank-name = "GPIOD";
+ status = "disabled";
+ };
+
+ gpioe: gpio@...80000 {
+ bootph-all;
+ reg = <0x40000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_GPIOE>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,bank-name = "GPIOE";
+ status = "disabled";
+ };
+
+ gpiof: gpio@...90000 {
+ bootph-all;
+ reg = <0x50000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_GPIOF>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,bank-name = "GPIOF";
+ status = "disabled";
+ };
+
+ gpiog: gpio@...a0000 {
+ bootph-all;
+ reg = <0x60000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_GPIOG>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,bank-name = "GPIOG";
+ status = "disabled";
+ };
+
+ gpioh: gpio@...b0000 {
+ bootph-all;
+ reg = <0x70000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_GPIOH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,bank-name = "GPIOH";
+ status = "disabled";
+ };
+
+ gpioi: gpio@...c0000 {
+ bootph-all;
+ reg = <0x80000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_GPIOI>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,bank-name = "GPIOI";
+ status = "disabled";
+ };
+ };
+
exti2: interrupt-controller@...d0000 {
compatible = "st,stm32mp1-exti", "syscon";
reg = <0x442d0000 0x0 0x400>;
@@ -267,6 +386,29 @@ exti2: interrupt-controller@...d0000 {
<&intc GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
};
+ pinctrl_z: pinctrl@...00000 {
+ bootph-all;
+ compatible = "st,stm32mp215-z-pinctrl";
+ ranges = <0 0x46200000 0x400>;
+ interrupt-parent = <&exti1>;
+ st,syscfg = <&exti1 0x60 0xff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpioz: gpio@...00000 {
+ bootph-all;
+ reg = <0 0x400>;
+ clocks = <&scmi_clk CK_SCMI_GPIOZ>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ status = "disabled";
+ };
+ };
+
intc: interrupt-controller@...10000 {
compatible = "arm,gic-400";
reg = <0x4ac10000 0x0 0x1000>,
--
2.34.1
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