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Message-ID: <CAAfSe-vS67E0pFgoDhVrpu6wh95P2SUemX+RgKKTSFUFYO+77A@mail.gmail.com>
Date: Tue, 18 Nov 2025 10:08:46 +0800
From: Chunyan Zhang <zhang.lyra@...il.com>
To: "Rob Herring (Arm)" <robh@...nel.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Orson Zhai <orsonzhai@...il.com>, Baolin Wang <baolin.wang@...ux.alibaba.com>,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: sprd: sc9860: Simplify clock nodes
On Wed, 29 Oct 2025 at 23:56, Rob Herring (Arm) <robh@...nel.org> wrote:
>
> The various "syscon" nodes in SC9860 are only referenced by clock
> provider nodes in a 1:1 relationship, and nothing else references the
> "syscon" nodes. There's no apparent reason for this split. The 2 nodes
> can simply be merged into 1 node. The clock driver has supported using
> either "reg" or "sprd,syscon" to access registers from the start, so
> there shouldn't be any compatibility issues.
>
> With this, DT schema warnings for missing a specific compatible with
> "syscon" and non-MMIO devices on "simple-bus" are fixed.
>
> Signed-off-by: Rob Herring (Arm) <robh@...nel.org>
Reviewed-by: Chunyan Zhang <zhang.lyra@...il.com>
> ---
> arch/arm64/boot/dts/sprd/sc9860.dtsi | 62 ----------------------------
> arch/arm64/boot/dts/sprd/whale2.dtsi | 54 ++++++++++++++++--------
> 2 files changed, 36 insertions(+), 80 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi
> index d2456d633c39..864ef0a17425 100644
> --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi
> +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi
> @@ -184,20 +184,6 @@ gic: interrupt-controller@...01000 {
> | IRQ_TYPE_LEVEL_HIGH)>;
> };
>
> - pmu_gate: pmu-gate {
> - compatible = "sprd,sc9860-pmu-gate";
> - sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
> - clocks = <&ext_26m>;
> - #clock-cells = <1>;
> - };
> -
> - pll: pll {
> - compatible = "sprd,sc9860-pll";
> - sprd,syscon = <&ana_regs>; /* 0x40400000 */
> - clocks = <&pmu_gate 0>;
> - #clock-cells = <1>;
> - };
> -
> ap_clk: clock-controller@...00000 {
> compatible = "sprd,sc9860-ap-clk";
> reg = <0 0x20000000 0 0x400>;
> @@ -214,19 +200,6 @@ aon_prediv: aon-prediv@...d0000 {
> #clock-cells = <1>;
> };
>
> - apahb_gate: apahb-gate {
> - compatible = "sprd,sc9860-apahb-gate";
> - sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */
> - clocks = <&aon_prediv 0>;
> - #clock-cells = <1>;
> - };
> -
> - aon_gate: aon-gate {
> - compatible = "sprd,sc9860-aon-gate";
> - sprd,syscon = <&aon_regs>; /* 0x402e0000 */
> - clocks = <&aon_prediv 0>;
> - #clock-cells = <1>;
> - };
>
> aonsecure_clk: clock-controller@...80000 {
> compatible = "sprd,sc9860-aonsecure-clk";
> @@ -235,13 +208,6 @@ aonsecure_clk: clock-controller@...80000 {
> #clock-cells = <1>;
> };
>
> - agcp_gate: agcp-gate {
> - compatible = "sprd,sc9860-agcp-gate";
> - sprd,syscon = <&agcp_regs>; /* 0x415e0000 */
> - clocks = <&aon_prediv 0>;
> - #clock-cells = <1>;
> - };
> -
> gpu_clk: clock-controller@...00000 {
> compatible = "sprd,sc9860-gpu-clk";
> reg = <0 0x60200000 0 0x400>;
> @@ -256,13 +222,6 @@ vsp_clk: clock-controller@...00000 {
> #clock-cells = <1>;
> };
>
> - vsp_gate: vsp-gate {
> - compatible = "sprd,sc9860-vsp-gate";
> - sprd,syscon = <&vsp_regs>; /* 0x61100000 */
> - clocks = <&vsp_clk 0>;
> - #clock-cells = <1>;
> - };
> -
> cam_clk: clock-controller@...00000 {
> compatible = "sprd,sc9860-cam-clk";
> reg = <0 0x62000000 0 0x4000>;
> @@ -270,13 +229,6 @@ cam_clk: clock-controller@...00000 {
> #clock-cells = <1>;
> };
>
> - cam_gate: cam-gate {
> - compatible = "sprd,sc9860-cam-gate";
> - sprd,syscon = <&cam_regs>; /* 0x62100000 */
> - clocks = <&cam_clk 0>;
> - #clock-cells = <1>;
> - };
> -
> disp_clk: clock-controller@...00000 {
> compatible = "sprd,sc9860-disp-clk";
> reg = <0 0x63000000 0 0x400>;
> @@ -284,20 +236,6 @@ disp_clk: clock-controller@...00000 {
> #clock-cells = <1>;
> };
>
> - disp_gate: disp-gate {
> - compatible = "sprd,sc9860-disp-gate";
> - sprd,syscon = <&disp_regs>; /* 0x63100000 */
> - clocks = <&disp_clk 0>;
> - #clock-cells = <1>;
> - };
> -
> - apapb_gate: apapb-gate {
> - compatible = "sprd,sc9860-apapb-gate";
> - sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */
> - clocks = <&ap_clk 0>;
> - #clock-cells = <1>;
> - };
> -
> funnel@...01000 { /* SoC Funnel */
> compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> reg = <0 0x10001000 0 0x1000>;
> diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi
> index a551e14ce826..dac2699a79d4 100644
> --- a/arch/arm64/boot/dts/sprd/whale2.dtsi
> +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi
> @@ -18,49 +18,67 @@ soc: soc {
> #size-cells = <2>;
> ranges;
>
> - ap_ahb_regs: syscon@...10000 {
> - compatible = "syscon";
> + apahb_gate: clock-controller@...10000 {
> reg = <0 0x20210000 0 0x10000>;
> + compatible = "sprd,sc9860-apahb-gate";
> + clocks = <&aon_prediv 0>;
> + #clock-cells = <1>;
> };
>
> - pmu_regs: syscon@...b0000 {
> - compatible = "syscon";
> + pmu_gate: clock-controller@...b0000 {
> reg = <0 0x402b0000 0 0x10000>;
> + compatible = "sprd,sc9860-pmu-gate";
> + clocks = <&ext_26m>;
> + #clock-cells = <1>;
> };
>
> - aon_regs: syscon@...e0000 {
> - compatible = "syscon";
> + aon_gate: clock-controller@...e0000 {
> reg = <0 0x402e0000 0 0x10000>;
> + compatible = "sprd,sc9860-aon-gate";
> + clocks = <&aon_prediv 0>;
> + #clock-cells = <1>;
> };
>
> - ana_regs: syscon@...00000 {
> - compatible = "syscon";
> + pll: clock-controller@...00000 {
> reg = <0 0x40400000 0 0x10000>;
> + compatible = "sprd,sc9860-pll";
> + clocks = <&pmu_gate 0>;
> + #clock-cells = <1>;
> };
>
> - agcp_regs: syscon@...e0000 {
> - compatible = "syscon";
> + agcp_gate: clock-controller@...e0000 {
> reg = <0 0x415e0000 0 0x1000000>;
> + compatible = "sprd,sc9860-agcp-gate";
> + clocks = <&aon_prediv 0>;
> + #clock-cells = <1>;
> };
>
> - vsp_regs: syscon@...00000 {
> - compatible = "syscon";
> + vsp_gate: clock-controller@...00000 {
> reg = <0 0x61100000 0 0x10000>;
> + compatible = "sprd,sc9860-vsp-gate";
> + clocks = <&vsp_clk 0>;
> + #clock-cells = <1>;
> };
>
> - cam_regs: syscon@...00000 {
> - compatible = "syscon";
> + cam_gate: clock-controller@...00000 {
> reg = <0 0x62100000 0 0x10000>;
> + compatible = "sprd,sc9860-cam-gate";
> + clocks = <&cam_clk 0>;
> + #clock-cells = <1>;
> };
>
> - disp_regs: syscon@...00000 {
> - compatible = "syscon";
> + disp_gate: clock-controller@...00000 {
> reg = <0 0x63100000 0 0x10000>;
> + compatible = "sprd,sc9860-disp-gate";
> + clocks = <&disp_clk 0>;
> + #clock-cells = <1>;
> };
>
> - ap_apb_regs: syscon@...00000 {
> - compatible = "syscon";
> + apapb_gate: clock-controller@...00000 {
> reg = <0 0x70b00000 0 0x40000>;
> + compatible = "sprd,sc9860-apapb-gate";
> + clocks = <&ap_clk 0>;
> + #clock-cells = <1>;
> };
>
> ap-apb@...00000 {
> --
> 2.51.0
>
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