linux-kernel - Re: [PATCH 2/4 v5] PCI: dw: Add more registers and bitfield definition

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Message-ID: <aRykzbnsMFFb1Kbo@lizhi-Precision-Tower-5810>
Date: Tue, 18 Nov 2025 11:54:37 -0500
From: Frank Li <Frank.li@....com>
To: Vincent Guittot <vincent.guittot@...aro.org>
Cc: chester62515@...il.com, mbrugger@...e.com,
	ghennadi.procopciuc@....nxp.com, s32@....com, bhelgaas@...gle.com,
	jingoohan1@...il.com, lpieralisi@...nel.org, kwilczynski@...nel.org,
	mani@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
	conor+dt@...nel.org, Ionut.Vicovan@....com, larisa.grigore@....com,
	Ghennadi.Procopciuc@....com, ciprianmarian.costea@....com,
	bogdan.hamciuc@....com, linux-arm-kernel@...ts.infradead.org,
	linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, imx@...ts.linux.dev,
	cassel@...nel.org
Subject: Re: [PATCH 2/4 v5] PCI: dw: Add more registers and bitfield
 definition

On Tue, Nov 18, 2025 at 05:02:36PM +0100, Vincent Guittot wrote:
> Add new registers and bitfield definition:
> - GEN3_RELATED_OFF_EQ_PHASE_2_3 field of GEN3_RELATED_OFF
> - 3 Coherency control registers
>
> Signed-off-by: Vincent Guittot <vincent.guittot@...aro.org>
> ---
Reviewed-by: Frank Li <Frank.Li@....com>
>  drivers/pci/controller/dwc/pcie-designware.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index e995f692a1ec..e60b77f1b5e6 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -121,6 +121,7 @@
>
>  #define GEN3_RELATED_OFF			0x890
>  #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL	BIT(0)
> +#define GEN3_RELATED_OFF_EQ_PHASE_2_3		BIT(9)
>  #define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS	BIT(13)
>  #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE	BIT(16)
>  #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT	24
> @@ -138,6 +139,13 @@
>  #define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA	GENMASK(13, 10)
>  #define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA	GENMASK(17, 14)
>
> +#define COHERENCY_CONTROL_1_OFF			0x8E0
> +#define CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK	GENMASK(31, 2)
> +#define CFG_MEMTYPE_VALUE			BIT(0)
> +
> +#define COHERENCY_CONTROL_2_OFF			0x8E4
> +#define COHERENCY_CONTROL_3_OFF			0x8E8
> +
>  #define PCIE_PORT_MULTI_LANE_CTRL	0x8C0
>  #define PORT_MLTI_UPCFG_SUPPORT		BIT(7)
>
> --
> 2.43.0
>