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Message-ID: <71e0d879-63ed-49e7-9bfe-c5cd8e0ca8ba@oss.qualcomm.com>
Date: Tue, 18 Nov 2025 14:44:22 +0800
From: Jingyi Wang <jingyi.wang@....qualcomm.com>
To: Taniya Das <taniya.das@....qualcomm.com>,
Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: aiqun.yu@....qualcomm.com, Ajit Pandey <ajit.pandey@....qualcomm.com>,
Imran Shaik <imran.shaik@....qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@....qualcomm.com>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 5/6] clk: qcom: Add TCSR clock driver for Kaanapali
On 10/30/2025 7:09 PM, Taniya Das wrote:
> Add the TCSR clock controller that provides the refclks on Kaanapali
> platform for PCIe, USB and UFS subsystems.
>
> Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
> Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> ---
> drivers/clk/qcom/Kconfig | 8 ++
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/tcsrcc-kaanapali.c | 141 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 150 insertions(+)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 4a78099e706c2cee5162d837cad3723db75039d0..8ec1803af76cb87da59ca3ef28127c06f3e26d2b 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -46,6 +46,14 @@ config CLK_GLYMUR_TCSRCC
> Support for the TCSR clock controller on GLYMUR devices.
> Say Y if you want to use peripheral devices such as USB/PCIe/EDP.
>
> +config CLK_KAANAPALI_TCSRCC
> + tristate "KAANAPALI TCSR Clock Controller"
> + depends on ARM64 || COMPILE_TEST
> + select QCOM_GDSC
> + help
> + Support for the TCSR clock controller on Kaanapali devices.
> + Say Y if you want to use peripheral devices such as PCIe, USB, UFS.
> +
> config CLK_X1E80100_CAMCC
> tristate "X1E80100 Camera Clock Controller"
> depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 5a0fd1d843c87a6f0a805706fcfad91c3f705340..2350631814779ad086d5c8304b250b0cc2f5203b 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
> obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
> obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
> obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
> +obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
> obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
> obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
> obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
> diff --git a/drivers/clk/qcom/tcsrcc-kaanapali.c b/drivers/clk/qcom/tcsrcc-kaanapali.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..14cfa75e892cc5ee1b03909f8c03d92de8ae2cd6
> --- /dev/null
> +++ b/drivers/clk/qcom/tcsrcc-kaanapali.c
> @@ -0,0 +1,141 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
> +
> +#include "clk-branch.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "common.h"
> +
> +enum {
> + DT_BI_TCXO_PAD,
> +};
> +
> +static struct clk_branch tcsr_pcie_0_clkref_en = {
> + .halt_reg = 0x0,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x0,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "tcsr_pcie_0_clkref_en",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
Hi Taniya,
Here is a discussion for tcsr in this thread:
https://lore.kernel.org/all/01de9616-825b-4fbb-83cf-e0bf91e8cf39@oss.qualcomm.com/
As TCSR_CLKS is a part of tcsr block, we should merge it as one node, the address
should be start at 0x01fc0000 instead of 0x01fd5044, so offset need to be added in the
tcsrcc reg configuration.
Thanks,
Jingyi
> +static struct clk_branch tcsr_ufs_clkref_en = {
> + .halt_reg = 0x10,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x10,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "tcsr_ufs_clkref_en",
> + .parent_data = &(const struct clk_parent_data){
> + .index = DT_BI_TCXO_PAD,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch tcsr_usb2_clkref_en = {
> + .halt_reg = 0x18,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x18,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "tcsr_usb2_clkref_en",
> + .parent_data = &(const struct clk_parent_data){
> + .index = DT_BI_TCXO_PAD,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch tcsr_usb3_clkref_en = {
> + .halt_reg = 0x8,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x8,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "tcsr_usb3_clkref_en",
> + .parent_data = &(const struct clk_parent_data){
> + .index = DT_BI_TCXO_PAD,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap *tcsr_cc_kaanapali_clocks[] = {
> + [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
> + [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
> + [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
> + [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
> +};
> +
> +static const struct regmap_config tcsr_cc_kaanapali_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x18,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc tcsr_cc_kaanapali_desc = {
> + .config = &tcsr_cc_kaanapali_regmap_config,
> + .clks = tcsr_cc_kaanapali_clocks,
> + .num_clks = ARRAY_SIZE(tcsr_cc_kaanapali_clocks),
> +};
> +
> +static const struct of_device_id tcsr_cc_kaanapali_match_table[] = {
> + { .compatible = "qcom,kaanapali-tcsr" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, tcsr_cc_kaanapali_match_table);
> +
> +static int tcsr_cc_kaanapali_probe(struct platform_device *pdev)
> +{
> + return qcom_cc_probe(pdev, &tcsr_cc_kaanapali_desc);
> +}
> +
> +static struct platform_driver tcsr_cc_kaanapali_driver = {
> + .probe = tcsr_cc_kaanapali_probe,
> + .driver = {
> + .name = "tcsr_cc-kaanapali",
> + .of_match_table = tcsr_cc_kaanapali_match_table,
> + },
> +};
> +
> +static int __init tcsr_cc_kaanapali_init(void)
> +{
> + return platform_driver_register(&tcsr_cc_kaanapali_driver);
> +}
> +subsys_initcall(tcsr_cc_kaanapali_init);
> +
> +static void __exit tcsr_cc_kaanapali_exit(void)
> +{
> + platform_driver_unregister(&tcsr_cc_kaanapali_driver);
> +}
> +module_exit(tcsr_cc_kaanapali_exit);
> +
> +MODULE_DESCRIPTION("QTI TCSR_CC KAANAPALI Driver");
> +MODULE_LICENSE("GPL");
>
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