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Message-ID: <5z5sqc5q547f4tb5selh6xwtiinjrsz5xx7jlvm7nchjhso3q5@ajli73mmj5cl>
Date: Tue, 18 Nov 2025 13:00:21 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Ziyue Zhang <ziyue.zhang@....qualcomm.com>, andersson@...nel.org,
        konradybcio@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
        conor+dt@...nel.org, jingoohan1@...il.com, mani@...nel.org,
        lpieralisi@...nel.org, kwilczynski@...nel.org, bhelgaas@...gle.com,
        johan+linaro@...nel.org, vkoul@...nel.org, kishon@...nel.org,
        neil.armstrong@...aro.org, abel.vesa@...aro.org, kw@...ux.com,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
        linux-phy@...ts.infradead.org, qiang.yu@....qualcomm.com,
        krishna.chundru@....qualcomm.com, quic_vbadigan@...cinc.com
Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: Add PCIe3 and PCIe5 regulators
 for HAMAO-IOT-EVK board

On Tue, Nov 18, 2025 at 11:23:43AM +0100, Konrad Dybcio wrote:
> On 11/18/25 11:11 AM, Ziyue Zhang wrote:
> > 
> > On 11/13/2025 5:16 AM, Dmitry Baryshkov wrote:
> >> On Wed, Nov 12, 2025 at 05:03:16PM +0800, Ziyue Zhang wrote:
> >>> HAMAO IoT EVK uses PCIe5 to connect an SDX65 module for WWAN functionality
> >>> and PCIe3 to connect a SATA controller. These interfaces require multiple
> >>> voltage rails: PCIe5 needs 3.3V supplied by vreg_wwan, while PCIe3 requires
> >>> 12V, 3.3V, and 3.3V AUX rails, controlled via PMIC GPIOs.
> >>>
> >>> Add the required fixed regulators with related pin configuration, and
> >>> connect them to the PCIe3 and PCIe5 ports to ensure proper power for the
> >>> SDX65 module and SATA controller.
> >>>
> >>> Signed-off-by: Ziyue Zhang <ziyue.zhang@....qualcomm.com>
> >>> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
> >>> ---
> >>>   arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 83 ++++++++++++++++++++++
> >>>   1 file changed, 83 insertions(+)
> >>>
> >>> +&pmc8380_3_gpios {
> >>> +    pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state {
> >> What is sde7? Other than that:
> >>
> >>
> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
> >>
> > Hi Dmitry
> > 
> > I’m not sure what “sde7” refers to specifically. I saw this name in the
> 
> It refers to "SD Express" which was connected to that PCIe host on some
> flavors of the internal boards, and the naming must have stuck..

Thanks!


Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>



-- 
With best wishes
Dmitry

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