lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID:
 <GV2PR04MB117402140ABAB3F2428C8120B96D7A@GV2PR04MB11740.eurprd04.prod.outlook.com>
Date: Wed, 19 Nov 2025 15:19:55 +0000
From: Claudiu Manoil <claudiu.manoil@....com>
To: Wei Fang <wei.fang@....com>, Vladimir Oltean <vladimir.oltean@....com>,
	Clark Wang <xiaoning.wang@....com>, "andrew+netdev@...n.ch"
	<andrew+netdev@...n.ch>, "davem@...emloft.net" <davem@...emloft.net>,
	"edumazet@...gle.com" <edumazet@...gle.com>, "kuba@...nel.org"
	<kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>
CC: Aziz Sellami <aziz.sellami@....com>, "imx@...ts.linux.dev"
	<imx@...ts.linux.dev>, "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v3 net-next 3/3] net: enetc: update the base address of
 port MDIO registers for ENETC v4

> -----Original Message-----
> From: Wei Fang <wei.fang@....com>
> Sent: Wednesday, November 19, 2025 12:26 PM
[...]
> Subject: [PATCH v3 net-next 3/3] net: enetc: update the base address of port
> MDIO registers for ENETC v4
> 
> Each ENETC has a set of external MDIO registers to access its external
> PHY based on its port EMDIO bus, these registers are used for MDIO bus
> access, such as setting the PHY address, PHY register address and value,
> read or write operations, C22 or C45 format, etc. The base address of
> this set of registers has been modified in ENETC v4 and is different
> from that in ENETC v1. So the base address needs to be updated so that
> ENETC v4 can use port MDIO to manage its own external PHY.
> 
> Additionally, if ENETC has the PCS layer, it also has a set of internal
> MDIO registers for managing its on-die PHY (PCS/Serdes). The base address
> of this set of registers is also different from that of ENETC v1, so the
> base address also needs to be updated so that ENETC v4 can support the
> management of on-die PHY through the internal MDIO bus.
> 
> Signed-off-by: Wei Fang <wei.fang@....com>
> ---

Reviewed-by: Claudiu Manoil <claudiu.manoil@....com>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ