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Message-ID: <50bd3be1-63dd-4bf5-915a-02d923fb0376@oss.qualcomm.com>
Date: Wed, 19 Nov 2025 23:36:24 +0530
From: Charan Teja Kalla <charan.kalla@....qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Cc: konrad.dybcio@....qualcomm.com, robin.clark@....qualcomm.com,
will@...nel.org, robin.murphy@....com, joro@...tes.org,
iommu@...ts.linux.dev, linux-arm-msm@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2] iommu/arm-smmu: add actlr settings for mdss on sa8775p
platform
On 11/18/2025 11:33 PM, Dmitry Baryshkov wrote:
>> Add ACTLR settings for the mdss device on Qualcomm SA8775P platform.
>> This is achieved by adding compatibility string for mdss in the actlr
>> client of match table.
>>
>> Signed-off-by: Charan Teja Kalla <charan.kalla@....qualcomm.com>
>> ---
>>
>> Changed from V1:
>> 1) Added actlr setting only for MDSS and dropped for fastrpc. -- konrad
>> 2) ACTLR table is updated per alphanumeric order -- konrad
>> https://lore.kernel.org/all/20251105075307.1658329-1-
>> charan.kalla@....qualcomm.com/
>>
>> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> index 62874b18f645..0b400e22cb00 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> @@ -41,6 +41,8 @@ static const struct of_device_id qcom_smmu_actlr_client_of_match[] = {
>> .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
>> { .compatible = "qcom,fastrpc",
>> .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
>> + { .compatible = "qcom,sa8775p-mdss",
>> + .data = (const void *) (PREFETCH_DEFAULT | CMTLB) },
> What's the difference from SC7280? Why don't we need to set CPRE?
Sorry, I'm really not sure If your question imply to talk about the IP
level difference compared to SC7280 for mdss?
Regarding why don't we need CPRE -- these are QoS settings that does
control how well hw behaves i.e., related to performance settings not
the functional ones. I guess, these settings are derived from factors
like how many masters are sharing a TBU, how crucial are masters using
that TBU(like important ones may be allowed to +7 or +15 and may be
others upto only +1 prefetch).
Thanks,
Charan
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