linux-kernel - [PATCH v5 2/8] dt-bindings: PCI: Add ASPEED PCIe RC support

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Message-ID:
 <SEYPR06MB51347EB7A223723DF021EFAE9DD7A@SEYPR06MB5134.apcprd06.prod.outlook.com>
Date: Wed, 19 Nov 2025 03:11:33 +0000
From: Jacky Chou <jacky_chou@...eedtech.com>
To: Rob Herring <robh@...nel.org>
CC: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
	Joel Stanley <joel@....id.au>, Andrew Jeffery <andrew@...econstruct.com.au>,
	Bjorn Helgaas <bhelgaas@...gle.com>, Lorenzo Pieralisi
	<lpieralisi@...nel.org>, Krzysztof Wilczyński
	<kwilczynski@...nel.org>, Manivannan Sadhasivam <mani@...nel.org>, Linus
 Walleij <linus.walleij@...aro.org>, Philipp Zabel <p.zabel@...gutronix.de>,
	"linux-aspeed@...ts.ozlabs.org" <linux-aspeed@...ts.ozlabs.org>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, Andrew Jeffery <andrew@...id.au>,
	"openbmc@...ts.ozlabs.org" <openbmc@...ts.ozlabs.org>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>
Subject: [PATCH v5 2/8] dt-bindings: PCI: Add ASPEED PCIe RC support

Hi Rob,

> > +
> > +      pcie@8,0 {
> 
> This node and the properties need to be in the schema along with a ref to
> pci-pci-bridge.yaml.
> 

Thank you for your information

> > +        reg = <0x804000 0 0 0 0>;
> 
> The address should not have the bus number as it is dynamic.
> 

Agreed.
The bus range is 0x00 to 0xFF. I will modify it in next version.

> > +        #address-cells = <3>;
> > +        #size-cells = <2>;
> > +        device_type = "pci";
> > +        resets = <&syscon ASPEED_RESET_PCIE_RC_O>;
> > +        reset-names = "perst";
> 
> Not sure this name is correct. PERST is a signal on the connector going
> downstream to the endpoint.
>

The reset property actually controls the PERST pin on this port.
At the same time, it also reset this port.

Therefore, here uses the "perst" name.

> > +        clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
> > +        pinctrl-names = "default";
> > +        pinctrl-0 = <&pinctrl_pcierc1_default>;
> > +        phys = <&pcie_phy1>;
> > +        ranges;
> > +      };
> > +    };

Thanks,
Jacky