linux-kernel - Re: (subset) [PATCH v3 2/4] clk: samsung: Add clock PLL support for ARTPEC-9 SoC

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Message-Id: <176355243758.116968.4431179201603632884.b4-ty@kernel.org>
Date: Wed, 19 Nov 2025 12:40:37 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, 
 jesper.nilsson@...s.com, lars.persson@...s.com, mturquette@...libre.com, 
 sboyd@...nel.org, alim.akhtar@...sung.com, s.nawrocki@...sung.com, 
 cw00.choi@...sung.com, Ravi Patel <ravi.patel@...sung.com>
Cc: ksk4725@...sia.com, smn1196@...sia.com, linux-arm-kernel@...s.com, 
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
 linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org, 
 linux-clk@...r.kernel.org, pjsin865@...sia.com, gwk1013@...sia.com, 
 bread@...sia.com, jspark@...sia.com, limjh0823@...sia.com, 
 lightwise@...sia.com, hgkim05@...sia.com, mingyoungbo@...sia.com, 
 shradha.t@...sung.com, swathi.ks@...sung.com, kenkim@...sia.com
Subject: Re: (subset) [PATCH v3 2/4] clk: samsung: Add clock PLL support
 for ARTPEC-9 SoC


On Wed, 29 Oct 2025 18:37:29 +0530, Ravi Patel wrote:
> Add below clock PLL support for Axis ARTPEC-9 SoC platform:
> - pll_a9fracm: Integer PLL with mid frequency FVCO (800 to 6400 MHz)
>              This is used in ARTPEC-9 SoC for shared PLL
> 
> - pll_a9fraco: Integer/Fractional PLL with mid frequency FVCO
>              (600 to 2400 MHz)
>              This is used in ARTPEC-9 SoC for Audio PLL
> 
> [...]

Applied, thanks!

[2/4] clk: samsung: Add clock PLL support for ARTPEC-9 SoC
      (no commit info)

Best regards,
-- 
Krzysztof Kozlowski <krzk@...nel.org>