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Message-ID: <2eee6abb-f82b-470c-8d39-15f09ffea3d4@oracle.com>
Date: Wed, 19 Nov 2025 17:41:49 +0530
From: ALOK TIWARI <alok.a.tiwari@...cle.com>
To: Bhargava Marreddy <bhargava.marreddy@...adcom.com>, davem@...emloft.net,
edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
andrew+netdev@...n.ch, horms@...nel.org
Cc: netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
michael.chan@...adcom.com, pavan.chebbi@...adcom.com,
vsrama-krishna.nemani@...adcom.com, vikas.gupta@...adcom.com,
Rajashekar Hudumula <rajashekar.hudumula@...adcom.com>
Subject: Re: [External] : [v2, net-next 03/12] bng_en: Add RX support
On 11/15/2025 1:22 AM, Bhargava Marreddy wrote:
> Add support to receive packet using NAPI, build and deliver the skb to stack.
> With help of meta data available in completions, fill the appropriate
> information in skb.
>
> Signed-off-by: Bhargava Marreddy <bhargava.marreddy@...adcom.com>
> Reviewed-by: Vikas Gupta <vikas.gupta@...adcom.com>
> Reviewed-by: Rajashekar Hudumula <rajashekar.hudumula@...adcom.com>
> ---
> drivers/net/ethernet/broadcom/bnge/Makefile | 3 +-
> .../net/ethernet/broadcom/bnge/bnge_hw_def.h | 201 ++++++
> .../net/ethernet/broadcom/bnge/bnge_netdev.c | 111 +++-
> .../net/ethernet/broadcom/bnge/bnge_netdev.h | 60 +-
> .../net/ethernet/broadcom/bnge/bnge_txrx.c | 573 ++++++++++++++++++
> .../net/ethernet/broadcom/bnge/bnge_txrx.h | 83 +++
> 6 files changed, 1010 insertions(+), 21 deletions(-)
> create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h
> create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_txrx.c
> create mode 100644 drivers/net/ethernet/broadcom/bnge/bnge_txrx.h
>
> diff --git a/drivers/net/ethernet/broadcom/bnge/Makefile b/drivers/net/ethernet/broadcom/bnge/Makefile
> index f30db7e5f48..1fedd7a0f14 100644
> --- a/drivers/net/ethernet/broadcom/bnge/Makefile
> +++ b/drivers/net/ethernet/broadcom/bnge/Makefile
> @@ -10,4 +10,5 @@ bng_en-y := bnge_core.o \
> bnge_resc.o \
> bnge_netdev.o \
> bnge_ethtool.o \
> - bnge_link.o
> + bnge_link.o \
> + bnge_txrx.o
> diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h b/drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h
> new file mode 100644
> index 00000000000..d0b3d4bea93
> --- /dev/null
> +++ b/drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h
> @@ -0,0 +1,201 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright (c) 2025 Broadcom */
> +
> +#ifndef _BNGE_HW_DEF_H_
> +#define _BNGE_HW_DEF_H_
> +
> +struct tx_bd_ext {
> + __le32 tx_bd_hsize_lflags;
> + #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
> + #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
> + #define TX_BD_FLAGS_NO_CRC (1 << 2)
> + #define TX_BD_FLAGS_STAMP (1 << 3)
> + #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
> + #define TX_BD_FLAGS_LSO (1 << 5)
> + #define TX_BD_FLAGS_IPID_FMT (1 << 6)
> + #define TX_BD_FLAGS_T_IPID (1 << 7)
> + #define TX_BD_HSIZE (0xff << 16)
> + #define TX_BD_HSIZE_SHIFT 16
> +
> + __le32 tx_bd_mss;
> + __le32 tx_bd_cfa_action;
> + #define TX_BD_CFA_ACTION (0xffff << 16)
> + #define TX_BD_CFA_ACTION_SHIFT 16
> +
> + __le32 tx_bd_cfa_meta;
> + #define TX_BD_CFA_META_MASK 0xfffffff
> + #define TX_BD_CFA_META_VID_MASK 0xfff
> + #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
> + #define TX_BD_CFA_META_PRI_SHIFT 12
> + #define TX_BD_CFA_META_TPID_MASK (3 << 16)
> + #define TX_BD_CFA_META_TPID_SHIFT 16
> + #define TX_BD_CFA_META_KEY (0xf << 28)
> + #define TX_BD_CFA_META_KEY_SHIFT 28
> + #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
> +};
> +
> +#define TX_CMP_SQ_CONS_IDX(txcmp) \
> + (le32_to_cpu((txcmp)->sq_cons_idx) & TX_CMP_SQ_CONS_IDX_MASK)
> +
> +struct rx_cmp {
> + __le32 rx_cmp_len_flags_type;
> + #define RX_CMP_CMP_TYPE (0x3f << 0)
> + #define RX_CMP_FLAGS_ERROR (1 << 6)
> + #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
> + #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
> + #define RX_CMP_FLAGS_PKT_METADATA_PRESENT (1 << 11)
> + #define RX_CMP_FLAGS_ITYPES_SHIFT 12
> + #define RX_CMP_FLAGS_ITYPES_MASK 0xf000
> + #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
> + #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
> + #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
> + #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
> + #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
> + #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
> + #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
> + #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
> + #define RX_CMP_LEN (0xffff << 16)
> + #define RX_CMP_LEN_SHIFT 16
> +
> + u32 rx_cmp_opaque;
> + __le32 rx_cmp_misc_v1;
> + #define RX_CMP_V1 (1 << 0)
> + #define RX_CMP_AGG_BUFS (0x1f << 1)
> + #define RX_CMP_AGG_BUFS_SHIFT 1
> + #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
> + #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
> + #define RX_CMP_V3_RSS_EXT_OP_LEGACY (0xf << 12)
> + #define RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT 12
> + #define RX_CMP_V3_RSS_EXT_OP_NEW (0xf << 8)
> + #define RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT 8
> + #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
> + #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
> + #define RX_CMP_SUB_NS_TS (0xf << 16)
> + #define RX_CMP_SUB_NS_TS_SHIFT 16
> + #define RX_CMP_METADATA1 (0xf << 28)
> + #define RX_CMP_METADATA1_SHIFT 28
> + #define RX_CMP_METADATA1_TPID_SEL (0x7 << 28)
> + #define RX_CMP_METADATA1_TPID_8021Q (0x1 << 28)
> + #define RX_CMP_METADATA1_TPID_8021AD (0x0 << 28)
> + #define RX_CMP_METADATA1_VALID (0x8 << 28)
> +
> + __le32 rx_cmp_rss_hash;
> +};
> +
> +struct rx_cmp_ext {
> + __le32 rx_cmp_flags2;
> + #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
> + #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
> + #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
> + #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
> + #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
> + __le32 rx_cmp_meta_data;
> + #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
> + #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
> + #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
> + #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
> + __le32 rx_cmp_cfa_code_errors_v2;
> + #define RX_CMP_V (1 << 0)
> + #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
> + #define RX_CMPL_ERRORS_SFT 1
> + #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
> + #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
> + #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
> + #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
> + #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
> + #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
> + #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
> + #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
> + #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
> + #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
> + #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
> + #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
> + #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
> + #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
> + #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
> + #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
> + #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
> + #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
> + #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
> + #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
> + #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
> + #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
> + #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
> + #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
> + #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
> + #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
> + #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
> + #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
> +
> + #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
> + #define RX_CMPL_CFA_CODE_SFT 16
> + #define RX_CMPL_METADATA0_TCI_MASK (0xffff << 16)
> + #define RX_CMPL_METADATA0_VID_MASK (0x0fff << 16)
> + #define RX_CMPL_METADATA0_SFT 16
> +
> + __le32 rx_cmp_timestamp;
> +};
> +
> +#define RX_CMP_L2_ERRORS \
> + cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
defined twice
> +
> +#define RX_CMP_L4_CS_BITS \
> + (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
> +
> +#define RX_CMP_L4_CS_ERR_BITS \
> + (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
> +
> +#define RX_CMP_L4_CS_OK(rxcmp1) \
> + (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
> + !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
> +
> +#define RX_CMP_METADATA0_TCI(rxcmp1) \
> + ((le32_to_cpu((rxcmp1)->rx_cmp_cfa_code_errors_v2) & \
> + RX_CMPL_METADATA0_TCI_MASK) >> RX_CMPL_METADATA0_SFT)
> +
> +#define RX_CMP_ENCAP(rxcmp1) \
> + ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
> + RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
> +
> +#define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp) \
> + ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & \
> + RX_CMP_V3_RSS_EXT_OP_LEGACY) >> RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT)
> +
> +#define RX_CMP_V3_HASH_TYPE_NEW(rxcmp) \
> + ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_NEW) >>\
> + RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT)
> +
> +#define RX_CMP_V3_HASH_TYPE(bd, rxcmp) \
> + (((bd)->rss_cap & BNGE_RSS_CAP_RSS_TCAM) ? \
> + RX_CMP_V3_HASH_TYPE_NEW(rxcmp) : \
> + RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp))
> +
> +#define EXT_OP_INNER_4 0x0
> +#define EXT_OP_OUTER_4 0x2
> +#define EXT_OP_INNFL_3 0x8
> +#define EXT_OP_OUTFL_3 0xa
> +
> +#define RX_CMP_VLAN_VALID(rxcmp) \
> + ((rxcmp)->rx_cmp_misc_v1 & cpu_to_le32(RX_CMP_METADATA1_VALID))
> +
> +#define RX_CMP_VLAN_TPID_SEL(rxcmp) \
> + (le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_METADATA1_TPID_SEL)
> +
> +#define RSS_PROFILE_ID_MASK 0x1f
> +
> +#define RX_CMP_HASH_TYPE(rxcmp) \
> + (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
> + RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
> +
> +#define RX_CMP_L2_ERRORS \
> + cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
redefine
> +
> +#define RX_CMP_HASH_VALID(rxcmp) \
> + ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
> +
> +#define HWRM_RING_ALLOC_TX 0x1
> +#define HWRM_RING_ALLOC_RX 0x2
> +#define HWRM_RING_ALLOC_AGG 0x4
> +#define HWRM_RING_ALLOC_CMPL 0x8
> +#define HWRM_RING_ALLOC_NQ 0x10
> +#endif /* _BNGE_HW_DEF_H_ */
> diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_netdev.c b/drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
> index 8785bf57d82..d7149f098a5 100644
> --- a/drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
> +++ b/drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
> @@ -21,6 +21,7 @@
> #include "bnge_hwrm_lib.h"
> #include "bnge_ethtool.h"
> #include "bnge_rmem.h"
> +#include "bnge_txrx.h"
>
> #define BNGE_RING_TO_TC_OFF(bd, tx) \
> ((tx) % (bd)->tx_nr_rings_per_tc)
> @@ -857,6 +858,13 @@ u16 bnge_cp_ring_for_tx(struct bnge_tx_ring_info *txr)
> return txr->tx_cpr->ring_struct.fw_ring_id;
> }
>
> +static void bnge_db_nq_arm(struct bnge_net *bn,
> + struct bnge_db_info *db, u32 idx)
> +{
> + bnge_writeq(bn->bd, db->db_key64 | DBR_TYPE_NQ_ARM |
> + DB_RING_IDX(db, idx), db->doorbell);
> +}
> +
> static void bnge_db_nq(struct bnge_net *bn, struct bnge_db_info *db, u32 idx)
> {
> bnge_writeq(bn->bd, db->db_key64 | DBR_TYPE_NQ_MASK |
> @@ -879,12 +887,6 @@ static int bnge_cp_num_to_irq_num(struct bnge_net *bn, int n)
> return nqr->ring_struct.map_idx;
> }
>
> -static irqreturn_t bnge_msix(int irq, void *dev_instance)
> -{
> - /* NAPI scheduling to be added in a future patch */
> - return IRQ_HANDLED;
> -}
> -
> static void bnge_init_nq_tree(struct bnge_net *bn)
> {
> struct bnge_dev *bd = bn->bd;
> @@ -942,9 +944,8 @@ static u8 *__bnge_alloc_rx_frag(struct bnge_net *bn, dma_addr_t *mapping,
> return page_address(page) + offset;
> }
>
> -static int bnge_alloc_rx_data(struct bnge_net *bn,
> - struct bnge_rx_ring_info *rxr,
> - u16 prod, gfp_t gfp)
> +int bnge_alloc_rx_data(struct bnge_net *bn, struct bnge_rx_ring_info *rxr,
> + u16 prod, gfp_t gfp)
> {
> struct bnge_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[RING_RX(bn, prod)];
> struct rx_bd *rxbd;
> @@ -1756,6 +1757,78 @@ static int bnge_cfg_def_vnic(struct bnge_net *bn)
> return rc;
> }
>
> +static void bnge_disable_int(struct bnge_net *bn)
> +{
> + struct bnge_dev *bd = bn->bd;
> + int i;
> +
> + if (!bn->bnapi)
> + return;
> +
> + for (i = 0; i < bd->nq_nr_rings; i++) {
> + struct bnge_napi *bnapi = bn->bnapi[i];
> + struct bnge_nq_ring_info *nqr = &bnapi->nq_ring;
> + struct bnge_ring_struct *ring = &nqr->ring_struct;
> +
> + if (ring->fw_ring_id != INVALID_HW_RING_ID)
> + bnge_db_nq(bn, &nqr->nq_db, nqr->nq_raw_cons);
> + }
> +}
> +
> +static void bnge_disable_int_sync(struct bnge_net *bn)
> +{
> + struct bnge_dev *bd = bn->bd;
> + int i;
> +
> + bnge_disable_int(bn);
> + for (i = 0; i < bd->nq_nr_rings; i++) {
> + int map_idx = bnge_cp_num_to_irq_num(bn, i);
> +
> + synchronize_irq(bd->irq_tbl[map_idx].vector);
> + }
> +}
> +
> +static void bnge_enable_int(struct bnge_net *bn)
> +{
> + struct bnge_dev *bd = bn->bd;
> + int i;
> +
> + for (i = 0; i < bd->nq_nr_rings; i++) {
> + struct bnge_napi *bnapi = bn->bnapi[i];
> + struct bnge_nq_ring_info *nqr = &bnapi->nq_ring;
> +
> + bnge_db_nq_arm(bn, &nqr->nq_db, nqr->nq_raw_cons);
> + }
> +}
> +
> +static void bnge_disable_napi(struct bnge_net *bn)
> +{
> + struct bnge_dev *bd = bn->bd;
> + int i;
> +
> + if (test_and_set_bit(BNGE_STATE_NAPI_DISABLED, &bn->state))
> + return;
> +
> + for (i = 0; i < bd->nq_nr_rings; i++) {
> + struct bnge_napi *bnapi = bn->bnapi[i];
> +
> + napi_disable_locked(&bnapi->napi);
> + }
> +}
> +
> +static void bnge_enable_napi(struct bnge_net *bn)
> +{
> + struct bnge_dev *bd = bn->bd;
> + int i;
> +
> + clear_bit(BNGE_STATE_NAPI_DISABLED, &bn->state);
> + for (i = 0; i < bd->nq_nr_rings; i++) {
> + struct bnge_napi *bnapi = bn->bnapi[i];
> +
> + napi_enable_locked(&bnapi->napi);
> + }
> +}
> +
> static void bnge_hwrm_vnic_free(struct bnge_net *bn)
> {
> int i;
> @@ -1887,6 +1960,12 @@ static void bnge_hwrm_ring_free(struct bnge_net *bn, bool close_path)
> bnge_hwrm_rx_agg_ring_free(bn, &bn->rx_ring[i], close_path);
> }
>
> + /* The completion rings are about to be freed. After that the
> + * IRQ doorbell will not work anymore. So we need to disable
> + * IRQ here.
> + */
> + bnge_disable_int_sync(bn);
> +
> for (i = 0; i < bd->nq_nr_rings; i++) {
> struct bnge_napi *bnapi = bn->bnapi[i];
> struct bnge_nq_ring_info *nqr;
> @@ -2086,16 +2165,6 @@ static int bnge_init_chip(struct bnge_net *bn)
> return rc;
> }
>
> -static int bnge_napi_poll(struct napi_struct *napi, int budget)
> -{
> - int work_done = 0;
> -
> - /* defer NAPI implementation to next patch series */
> - napi_complete_done(napi, work_done);
> -
> - return work_done;
> -}
> -
> static void bnge_init_napi(struct bnge_net *bn)
> {
> struct bnge_dev *bd = bn->bd;
> @@ -2194,6 +2263,8 @@ static int bnge_open_core(struct bnge_net *bn)
> goto err_free_irq;
> }
>
> + bnge_enable_napi(bn);
> +
> mutex_lock(&bd->link_lock);
> rc = bnge_update_phy_setting(bn);
> mutex_unlock(&bd->link_lock);
> @@ -2208,6 +2279,7 @@ static int bnge_open_core(struct bnge_net *bn)
>
> set_bit(BNGE_STATE_OPEN, &bd->state);
>
> + bnge_enable_int(bn);
> /* Poll link status and check for SFP+ module status */
> mutex_lock(&bd->link_lock);
> bnge_get_port_module_status(bn);
> @@ -2254,6 +2326,7 @@ static void bnge_close_core(struct bnge_net *bn)
>
> clear_bit(BNGE_STATE_OPEN, &bd->state);
> bnge_shutdown_nic(bn);
> + bnge_disable_napi(bn);
> bnge_free_all_rings_bufs(bn);
> bnge_free_irq(bn);
> bnge_del_napi(bn);
> diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_netdev.h b/drivers/net/ethernet/broadcom/bnge/bnge_netdev.h
> index b267f0b14c1..d13c0c52553 100644
> --- a/drivers/net/ethernet/broadcom/bnge/bnge_netdev.h
> +++ b/drivers/net/ethernet/broadcom/bnge/bnge_netdev.h
> @@ -9,6 +9,7 @@
> #include <linux/refcount.h>
> #include "bnge_db.h"
> #include "bnge_link.h"
> +#include "bnge_hw_def.h"
>
> struct tx_bd {
> __le32 tx_bd_len_flags_type;
> @@ -174,10 +175,16 @@ enum {
> #define RING_RX_AGG(bn, idx) ((idx) & (bn)->rx_agg_ring_mask)
> #define NEXT_RX_AGG(idx) ((idx) + 1)
>
> +#define BNGE_NQ_HDL_IDX_MASK 0x00ffffff
> +#define BNGE_NQ_HDL_TYPE_MASK 0xff000000
> #define BNGE_NQ_HDL_TYPE_SHIFT 24
> #define BNGE_NQ_HDL_TYPE_RX 0x00
> #define BNGE_NQ_HDL_TYPE_TX 0x01
>
> +#define BNGE_NQ_HDL_IDX(hdl) ((hdl) & BNGE_NQ_HDL_IDX_MASK)
> +#define BNGE_NQ_HDL_TYPE(hdl) (((hdl) & BNGE_NQ_HDL_TYPE_MASK) >> \
> + BNGE_NQ_HDL_TYPE_SHIFT)
> +
> struct bnge_net {
> struct bnge_dev *bd;
> struct net_device *netdev;
> @@ -235,6 +242,9 @@ struct bnge_net {
> u32 stats_coal_ticks;
>
> struct bnge_ethtool_link_info eth_link_info;
> +
> + unsigned long state;
> +#define BNGE_STATE_NAPI_DISABLED 0
> };
>
> #define BNGE_DEFAULT_RX_RING_SIZE 511
> @@ -281,9 +291,25 @@ void bnge_set_ring_params(struct bnge_dev *bd);
> txr = (iter < BNGE_MAX_TXR_PER_NAPI - 1) ? \
> (bnapi)->tx_ring[++iter] : NULL)
>
> +#define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \
> + ((db)->db_epoch_shift))
> +
> +#define DB_TOGGLE(tgl) ((tgl) << DBR_TOGGLE_SFT)
> +
> +#define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \
> + DB_EPOCH(db, idx))
> +
> #define BNGE_SET_NQ_HDL(cpr) \
> (((cpr)->cp_ring_type << BNGE_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)
>
> +#define BNGE_DB_NQ(db, idx) \
> + bnge_writeq(bd, (db)->db_key64 | DBR_TYPE_NQ | DB_RING_IDX(db, idx),\
> + (db)->doorbell)
no bd here, Pass bd as a macro argument.
> +
> +#define BNGE_DB_NQ_ARM(db, idx) \
> + bnge_writeq(bd, (db)->db_key64 | DBR_TYPE_NQ_ARM | \
> + DB_RING_IDX(db, idx), (db)->doorbell)
> +
> struct bnge_stats_mem {
> u64 *sw_stats;
> u64 *hw_masks;
> @@ -292,6 +318,25 @@ struct bnge_stats_mem {
> int len;
> };
>
> +struct nqe_cn {
> + __le16 type;
> + #define NQ_CN_TYPE_MASK 0x3fUL
> + #define NQ_CN_TYPE_SFT 0
> + #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
> + #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
> + #define NQ_CN_TOGGLE_MASK 0xc0UL
> + #define NQ_CN_TOGGLE_SFT 6
> + __le16 reserved16;
> + __le32 cq_handle_low;
> + __le32 v;
> + #define NQ_CN_V 0x1UL
> + __le32 cq_handle_high;
> +};
> +
> +#define NQE_CN_TYPE(type) ((type) & NQ_CN_TYPE_MASK)
> +#define NQE_CN_TOGGLE(type) (((type) & NQ_CN_TOGGLE_MASK) >> \
> + NQ_CN_TOGGLE_SFT)
> +
> struct bnge_cp_ring_info {
> struct bnge_napi *bnapi;
> dma_addr_t *desc_mapping;
> @@ -301,6 +346,10 @@ struct bnge_cp_ring_info {
> u8 cp_idx;
> u32 cp_raw_cons;
> struct bnge_db_info cp_db;
> + u8 had_work_done:1;
> + u8 has_more_work:1;
> + u8 had_nqe_notify:1;
> + u8 toggle;
> };
>
> struct bnge_nq_ring_info {
> @@ -313,8 +362,9 @@ struct bnge_nq_ring_info {
>
> struct bnge_stats_mem stats;
> u32 hw_stats_ctx_id;
> + u8 has_more_work:1;
>
> - int cp_ring_count;
> + u16 cp_ring_count;
> struct bnge_cp_ring_info *cp_ring_arr;
> };
>
> @@ -377,6 +427,12 @@ struct bnge_napi {
> struct bnge_nq_ring_info nq_ring;
> struct bnge_rx_ring_info *rx_ring;
> struct bnge_tx_ring_info *tx_ring[BNGE_MAX_TXR_PER_NAPI];
> + u8 events;
> +#define BNGE_RX_EVENT 1
> +#define BNGE_AGG_EVENT 2
> +#define BNGE_TX_EVENT 4
> +#define BNGE_REDIRECT_EVENT 8
> +#define BNGE_TX_CMP_EVENT 0x10
> };
>
> #define INVALID_STATS_CTX_ID -1
> @@ -455,4 +511,6 @@ struct bnge_l2_filter {
> u16 bnge_cp_ring_for_rx(struct bnge_rx_ring_info *rxr);
> u16 bnge_cp_ring_for_tx(struct bnge_tx_ring_info *txr);
> void bnge_fill_hw_rss_tbl(struct bnge_net *bn, struct bnge_vnic_info *vnic);
> +int bnge_alloc_rx_data(struct bnge_net *bn, struct bnge_rx_ring_info *rxr,
> + u16 prod, gfp_t gfp);
> #endif /* _BNGE_NETDEV_H_ */
> diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_txrx.h b/drivers/net/ethernet/broadcom/bnge/bnge_txrx.h
> new file mode 100644
> index 00000000000..f3e08064add
> --- /dev/null
> +++ b/drivers/net/ethernet/broadcom/bnge/bnge_txrx.h
> @@ -0,0 +1,83 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright (c) 2025 Broadcom */
> +
> +#ifndef _BNGE_TXRX_H_
> +#define _BNGE_TXRX_H_
> +
> +#include <linux/bnxt/hsi.h>
> +#include "bnge_netdev.h"
> +
> +#define BNGE_MIN_PKT_SIZE 52
> +
> +#define TX_OPAQUE_IDX_MASK 0x0000ffff
> +#define TX_OPAQUE_BDS_MASK 0x00ff0000
> +#define TX_OPAQUE_BDS_SHIFT 16
> +#define TX_OPAQUE_RING_MASK 0xff000000
> +#define TX_OPAQUE_RING_SHIFT 24
> +
> +#define SET_TX_OPAQUE(bn, txr, idx, bds) \
> + (((txr)->tx_napi_idx << TX_OPAQUE_RING_SHIFT) | \
> + ((bds) << TX_OPAQUE_BDS_SHIFT) | ((idx) & (bn)->tx_ring_mask))
> +
> +#define TX_OPAQUE_IDX(opq) ((opq) & TX_OPAQUE_IDX_MASK)
> +#define TX_OPAQUE_RING(opq) (((opq) & TX_OPAQUE_RING_MASK) >> \
> + TX_OPAQUE_RING_SHIFT)
> +#define TX_OPAQUE_BDS(opq) (((opq) & TX_OPAQUE_BDS_MASK) >> \
> + TX_OPAQUE_BDS_SHIFT)
> +#define TX_OPAQUE_PROD(bn, opq) ((TX_OPAQUE_IDX(opq) + TX_OPAQUE_BDS(opq)) &\
> + (bn)->tx_ring_mask)
> +
> +/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
> + * BD because the first TX BD is always a long BD.
> + */
> +#define BNGE_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
> +
> +#define RX_RING(bn, x) (((x) & (bn)->rx_ring_mask) >> (BNGE_PAGE_SHIFT - 4))
> +#define RX_AGG_RING(bn, x) (((x) & (bn)->rx_agg_ring_mask) >> \
> + (BNGE_PAGE_SHIFT - 4))
> +#define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
> +
> +#define TX_RING(bn, x) (((x) & (bn)->tx_ring_mask) >> (BNGE_PAGE_SHIFT - 4))
> +#define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
> +
> +#define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNGE_PAGE_SHIFT - 4))
> +#define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
> +
> +#define TX_CMP_VALID(txcmp, raw_cons) \
> + (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
> + !((raw_cons) & bn->cp_bit))
same bn
> +
> +#define RX_CMP_VALID(rxcmp1, raw_cons) \
> + (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
> + !((raw_cons) & bn->cp_bit))
> +
> +#define RX_AGG_CMP_VALID(agg, raw_cons) \
> + (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
> + !((raw_cons) & bn->cp_bit))
> +
> +#define NQ_CMP_VALID(nqcmp, raw_cons) \
> + (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bn->cp_bit))
> +
> +#define TX_CMP_TYPE(txcmp) \
> + (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
> +
> +#define RX_CMP_TYPE(rxcmp) \
> + (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
> +
> +#define RING_RX(bn, idx) ((idx) & (bn)->rx_ring_mask)
> +#define NEXT_RX(idx) ((idx) + 1)
> +
> +#define RING_RX_AGG(bn, idx) ((idx) & (bn)->rx_agg_ring_mask)
> +#define NEXT_RX_AGG(idx) ((idx) + 1)
> +
> +#define RING_TX(bn, idx) ((idx) & (bn)->tx_ring_mask)
> +#define NEXT_TX(idx) ((idx) + 1)
> +
> +#define ADV_RAW_CMP(idx, n) ((idx) + (n))
> +#define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
> +#define RING_CMP(bn, idx) ((idx) & (bn)->cp_ring_mask)
> +
> +irqreturn_t bnge_msix(int irq, void *dev_instance);
> +void bnge_reuse_rx_data(struct bnge_rx_ring_info *rxr, u16 cons, void *data);
> +int bnge_napi_poll(struct napi_struct *napi, int budget);
> +#endif /* _BNGE_TXRX_H_ */
Thanks,
Alok
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