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Message-ID: <gmmdmujfrnenxuvuohlg3xfyicauvk42rhdoe2ojnlfaa4ljck@x4wqnlkyqulb>
Date: Thu, 20 Nov 2025 21:34:32 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>,
bhelgaas@...gle.com, linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] PCI: Add quirk to disable ASPM L1 for Sandisk SN740 NVMe
SSDs
On Thu, Nov 20, 2025 at 04:50:44PM +0100, Konrad Dybcio wrote:
> On 11/20/25 4:46 PM, Manivannan Sadhasivam wrote:
> > The Sandisk SN740 NVMe SSDs cause below AER errors on the upstream Root
> > Port of PCIe controller in Lenovo Thinkpad T14s laptop when ASPM L1 is
>
> ^ Microsoft Surface Laptop 7
>
Err... Somehow I assumed that it was T14s ;)
@Bjorn: Let me know if I have to resend or you can fix it up while applying.
- Mani
> Konrad
>
> > enabled:
> >
> > pcieport 0006:00:00.0: AER: Correctable error message received from 0006:01:00.0
> > nvme 0006:01:00.0: PCIe Bus Error: severity=Correctable, type=Physical Layer, (Receiver ID)
> > nvme 0006:01:00.0: device [15b7:5015] error status/mask=00000001/0000e000
> > nvme 0006:01:00.0: [ 0] RxErr
> >
> > Hence, add a quirk to disable L1 state for this SSD.
> >
> > Reported-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> > Signed-off-by: Manivannan Sadhasivam <mani@...nel.org>
> > ---
> > drivers/pci/quirks.c | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index 214ed060ca1b..a6f88c5ba2f4 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -2525,6 +2525,18 @@ static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
> > */
> > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
> >
> > +static void quirk_disable_aspm_l1(struct pci_dev *dev)
> > +{
> > + pci_info(dev, "Disabling ASPM L1\n");
> > + pci_disable_link_state(dev, PCIE_LINK_STATE_L1);
> > +}
> > +
> > +/*
> > + * Sandisk SN740 NVMe SSDs cause AER timeout errors on the upstream PCIe Root
> > + * Port when ASPM L1 is enabled.
> > + */
> > +DECLARE_PCI_FIXUP_FINAL(0x15b7, 0x5015, quirk_disable_aspm_l1);
> > +
> > /*
> > * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
> > * Link bit cleared after starting the link retrain process to allow this
--
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