Message-Id: <20251120053431.491677-1-dapeng1.mi@linux.intel.com>
Date: Thu, 20 Nov 2025 13:34:24 +0800
From: Dapeng Mi <dapeng1.mi@...ux.intel.com>
To: Peter Zijlstra <peterz@...radead.org>,
	Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	Namhyung Kim <namhyung@...nel.org>,
	Ian Rogers <irogers@...gle.com>,
	Adrian Hunter <adrian.hunter@...el.com>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Andi Kleen <ak@...ux.intel.com>,
	Eranian Stephane <eranian@...gle.com>
Cc: linux-kernel@...r.kernel.org,
	linux-perf-users@...r.kernel.org,
	Dapeng Mi <dapeng1.mi@...el.com>,
	Zide Chen <zide.chen@...el.com>,
	Falcon Thomas <thomas.falcon@...el.com>,
	Xudong Hao <xudong.hao@...el.com>,
	Dapeng Mi <dapeng1.mi@...ux.intel.com>
Subject: [PATCH 0/7] Enable core PMU for DMR and NVL

This patch-set enables core PMU functionalities for Diamond Rapids (DMR)
and Nova Lake (NVL). 

Comparing with previous platforms, there are 3 main changes on core PMU
functionalities.

1. Introduce OFF-MODULE RESPONSE (OMR) facility to replace Off-Core
Response (OCR) facility

Legacy microarchitectures used the OCR facility to evaluate off-core and
multi-core off-module transactions. The properly renamed, OMR facility,
improves the OCR capability for scalable coverage of new memory systems
of multi-core module systems.

Along with the introduction of OMR, 4 equivalent MSRs (OFFMODULE_RSP_0 ~
OFFMODULE_RSP_3) are introduced to specify attributes of the off-module
transaction and the legacy 2 OFFCORE_RSP MSRs are retired.

For more details about OMR events and OFFMODULE_RSP_x MSRs, please refer
to the section 16.1 "OFF-MODULE RESPONSE (OMR) FACILITY" in latest ISE[1]
documentation.

2. New PEBS data source encoding layout

Diamond Rapids and Nova Lake include PEBS Load Latency and Store Latency
support similar to previous platforms but with a different data source
encoding layout.

Briefly speaking, the new data source encoding is determined by bit[8] of
memory auxiliary info field. The bit[8] indicates whether a L2 cache miss
occurs for a memory load or store instruction. If bit[8] is 0, it
signifies no L2 cache miss, and bits[7:0] specify the exact cache data
source (up to the L2 cache level). If bit[8] is 1, bits[7:0] represents
the OMR encoding, indicating the specific L3 cache or memory region
involved in the memory access.

A significant enhancement for OMR encoding is the ability to provide
up to 8 fine-grained memory regions in addition to the cache region,
offering more detailed insights into memory access regions.

For more details about the new data source layout, please refer to the
section 16.2 "PEBS LOAD LATENCY AND STORE LATENCY FACILITY" in latest
ISE documentation.

3. Support "rdpmc user disable" feature

Currently executing RDPMC when CPL > 0 is allowed if the CR4.PCE flag
(performance-monitoring counter enable) is set. This introduces a
security risk that any user space process can read the count of any PMU
counter even though the counter belongs to a system-wide event as long
as CR4.PCE = 1.

To mitigate this security risk, the rdpmc user disable feature is
introduced to provide per-counter rdpmc control.

'rdpmc user disable' introduces a new bit "RDPMC_USR_DISABLE" to manage
if the counter can be read in user space by leveraging rdpmc instruction
for each GP and fixed counter.

The details are
- New RDPMC_USR_DISABLE bit in each EVNTSELx[37] MSR to indicate counter
  can't be read by RDPMC in ring 3.
- New RDPMC_USR_DISABLE bits in bits 33,37,41,45,etc.,
  in IA32_FIXED_CTR_CTRL MSR for fixed counters 0-3, etc.
- On RDPMC for counter x, use select to choose the final counter value:
  If (!CPL0 && RDPMC_USR_DISABLE[x] == 1 ) ? 0 : counter_value
- RDPMC_USR_DISABLE is enumerated by CPUID.0x23.0.EBX[2].

For more details about "rdpmc user disable", please refer to chapter 15
"RDPMC USER DISABLE" in latest ISE.

This patch-set adds support for these 3 new changes or features. Besides
the DMR and NVL specific counter constraints are supported together.

Tests:

The below tests pass on DMR and NVL (both P-core and E-core).
 a) Perf counting tests pass.
 b) Perf sampling tests pass.
 c) Perf PEBS based sampling tests pass.
 d) "rdpmc user disable" functionality tests pass.

Ref:

ISE (version 60): https://www.intel.com/content/www/us/en/content-details/869288/intel-architecture-instruction-set-extensions-programming-reference.html 

Dapeng Mi (7):
  perf/x86/intel: Support newly introduced 4 OMR MSRs for DMR & NVL
  perf/x86/intel: Add support for PEBS memory auxiliary info field in
    DMR
  perf/x86/intel: Add core PMU support for DMR
  perf/x86/intel: Add support for PEBS memory auxiliary info field in
    NVL
  perf/x86/intel: Add core PMU support for Novalake
  perf/x86: Replace magic numbers with macros for attr_rdpmc
  perf/x86/intel: Add rdpmc-user-disable support

 .../sysfs-bus-event_source-devices-rdpmc      |  40 ++
 arch/x86/events/core.c                        |  28 +-
 arch/x86/events/intel/core.c                  | 352 +++++++++++++++++-
 arch/x86/events/intel/ds.c                    | 261 +++++++++++++
 arch/x86/events/intel/p6.c                    |   2 +-
 arch/x86/events/perf_event.h                  |  26 ++
 arch/x86/include/asm/msr-index.h              |   5 +
 arch/x86/include/asm/perf_event.h             |   8 +-
 include/uapi/linux/perf_event.h               |  27 +-
 tools/include/uapi/linux/perf_event.h         |  27 +-
 10 files changed, 751 insertions(+), 25 deletions(-)
 create mode 100644 Documentation/ABI/testing/sysfs-bus-event_source-devices-rdpmc


base-commit: 9929dffce5ed7e2988e0274f4db98035508b16d9
-- 
2.34.1

Powered by blists - more mailing lists