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Message-Id: <20251120081921.39412-9-wenliang202407@163.com>
Date: Thu, 20 Nov 2025 03:19:21 -0500
From: Wenliang Yan <wenliang202407@....com>
To: linux@...ck-us.net,
Jean Delvare <jdelvare@...e.com>
Cc: Wenliang Yan <wenliang202407@....com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Jonathan Corbet <corbet@....net>,
linux-hwmon@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v3 8/8] hwmon: (ina3221) Modify write/read functions for 'in' and 'curr' attribute
Modified the relevant read/write functions for 'in' and 'curr' attributes,
adding support for crit, lcrit, crit_alarm, and lcrit_alarm features.
Signed-off-by: Wenliang Yan <wenliang202407@....com>
---
drivers/hwmon/ina3221.c | 96 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 92 insertions(+), 4 deletions(-)
diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
index af6d9ca5ae28..5ffa0f622e25 100644
--- a/drivers/hwmon/ina3221.c
+++ b/drivers/hwmon/ina3221.c
@@ -380,6 +380,12 @@ static const u8 ina3221_in_reg[] = {
INA3221_SHUNT_SUM,
};
+static const u8 alert_flag[] = {
+ F_AFF1,
+ F_AFF2,
+ F_AFF3,
+};
+
static int ina3221_read_chip(struct device *dev, u32 attr, long *val)
{
struct ina3221_data *ina = dev_get_drvdata(dev);
@@ -442,6 +448,38 @@ static int ina3221_read_in(struct device *dev, u32 attr, int channel, long *val)
case hwmon_in_enable:
*val = ina3221_is_enabled(ina, channel);
return 0;
+ case hwmon_in_crit:
+ case hwmon_in_lcrit:
+ if (!ina3221_is_enabled(ina, channel))
+ return -ENODATA;
+
+ if (channel >= INA3221_NUM_CHANNELS)
+ return -EOPNOTSUPP;
+
+ reg = limit_regs[channel];
+ ret = ina3221_read_value(ina, reg, ®val);
+ if (ret)
+ return ret;
+ /*
+ * Scale of bus voltage (mV): LSB is 8mV
+ */
+ *val = regval * 8;
+ return 0;
+ case hwmon_in_crit_alarm:
+ case hwmon_in_lcrit_alarm:
+ /* No actual register read if channel is disabled */
+ if (!ina3221_is_enabled(ina, channel)) {
+ /* Return 0 for alert flags */
+ *val = 0;
+ return 0;
+ }
+
+ reg = alert_flag[channel];
+ ret = regmap_field_read(ina->fields[reg], ®val);
+ if (ret)
+ return ret;
+ *val = regval;
+ return 0;
default:
return -EOPNOTSUPP;
}
@@ -501,6 +539,25 @@ static int ina3221_read_curr(struct device *dev, u32 attr,
/* Return current in mA */
*val = DIV_ROUND_CLOSEST(voltage_nv, resistance_uo);
return 0;
+ case hwmon_curr_lcrit:
+ if (!resistance_uo)
+ return -ENODATA;
+
+ if (channel >= INA3221_NUM_CHANNELS)
+ return -EOPNOTSUPP;
+
+ reg = limit_regs[channel];
+ ret = ina3221_read_value(ina, reg, ®val);
+ if (ret)
+ return ret;
+
+ /* Return current in mA */
+ *val = DIV_ROUND_CLOSEST(regval * ina->current_lsb_uA, 1000);
+ return 0;
+ case hwmon_curr_lcrit_alarm:
+ reg = alert_flag[channel];
+
+ fallthrough;
case hwmon_curr_crit_alarm:
case hwmon_curr_max_alarm:
/* No actual register read if channel is disabled */
@@ -698,10 +755,9 @@ static int ina3221_write_chip(struct device *dev, u32 attr, long val)
}
}
-static int ina3221_write_curr(struct device *dev, u32 attr,
- int channel, long val)
+static int ina3221_write_curr_shunt(struct ina3221_data *ina, u32 attr,
+ int channel, long val)
{
- struct ina3221_data *ina = dev_get_drvdata(dev);
struct ina3221_input *input = ina->inputs;
u8 reg = ina3221_curr_reg[attr][channel];
int resistance_uo, current_ma, voltage_uv;
@@ -744,6 +800,22 @@ static int ina3221_write_curr(struct device *dev, u32 attr,
return regmap_write(ina->regmap, reg, regval);
}
+static int ina3221_write_curr(struct device *dev, u32 attr,
+ int channel, long val)
+{
+ struct ina3221_data *ina = dev_get_drvdata(dev);
+
+ switch (attr) {
+ case hwmon_curr_crit:
+ case hwmon_curr_max:
+ return ina3221_write_curr_shunt(ina, attr, channel, val);
+ case hwmon_curr_lcrit:
+ return sq52210_alert_limit_write(ina, SQ52210_ALERT_SUL, channel, val);
+ default:
+ return 0;
+ }
+}
+
static int ina3221_write_enable(struct device *dev, int channel, bool enable)
{
struct ina3221_data *ina = dev_get_drvdata(dev);
@@ -792,6 +864,22 @@ static int ina3221_write_enable(struct device *dev, int channel, bool enable)
return ret;
}
+static int ina3221_write_in(struct device *dev, u32 attr, int channel, long val)
+{
+ struct ina3221_data *ina = dev_get_drvdata(dev);
+
+ switch (attr) {
+ case hwmon_in_lcrit:
+ return sq52210_alert_limit_write(ina, SQ52210_ALERT_BUL, channel, val);
+ case hwmon_in_crit:
+ return sq52210_alert_limit_write(ina, SQ52210_ALERT_BOL, channel, val);
+ case hwmon_in_enable:
+ return ina3221_write_enable(dev, channel, val);
+ default:
+ return 0;
+ }
+}
+
static int ina3221_write_power(struct device *dev, u32 attr, int channel, long val)
{
struct ina3221_data *ina = dev_get_drvdata(dev);
@@ -841,7 +929,7 @@ static int ina3221_write(struct device *dev, enum hwmon_sensor_types type,
break;
case hwmon_in:
/* 0-align channel ID */
- ret = ina3221_write_enable(dev, channel - 1, val);
+ ret = ina3221_write_in(dev, attr, channel - 1, val);
break;
case hwmon_curr:
ret = ina3221_write_curr(dev, attr, channel, val);
--
2.17.1
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