linux-kernel - Re: [PATCH V2 11/14] LoongArch: Adjust misc routines for 32BIT/64BIT

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Message-ID: <CAAhV-H64h2AtMt-zZYLs7ZZAWadEpU=ZUpvPojC6ut-Z04YDdA@mail.gmail.com>
Date: Thu, 20 Nov 2025 20:04:13 +0800
From: Huacai Chen <chenhuacai@...nel.org>
To: WANG Xuerui <kernel@...0n.name>
Cc: Huacai Chen <chenhuacai@...ngson.cn>, Arnd Bergmann <arnd@...db.de>, loongarch@...ts.linux.dev, 
	linux-arch@...r.kernel.org, Xuefeng Li <lixuefeng@...ngson.cn>, 
	Guo Ren <guoren@...nel.org>, Jiaxun Yang <jiaxun.yang@...goat.com>, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 11/14] LoongArch: Adjust misc routines for 32BIT/64BIT

On Thu, Nov 20, 2025 at 6:45 PM WANG Xuerui <kernel@...0n.name> wrote:
>
> On 11/18/25 19:27, Huacai Chen wrote:
> > Adjust misc routines for both 32BIT and 64BIT, including: checksum,
> > jump label, unaligned access emulator, PCI init routines, sleep/wakeup
> > routines, etc.
> >
> > Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com>
> > Signed-off-by: Huacai Chen <chenhuacai@...ngson.cn>
> > ---
> >   arch/loongarch/include/asm/checksum.h   |  4 ++
> >   arch/loongarch/include/asm/jump_label.h | 12 ++++-
> >   arch/loongarch/include/asm/string.h     |  2 +
> >   arch/loongarch/kernel/unaligned.c       | 30 ++++++++---
> >   arch/loongarch/lib/unaligned.S          | 72 ++++++++++++-------------
> >   arch/loongarch/pci/pci.c                |  8 +--
> >   arch/loongarch/power/suspend_asm.S      | 72 ++++++++++++-------------
> >   7 files changed, 116 insertions(+), 84 deletions(-)
> >
> > [snip]
> > diff --git a/arch/loongarch/pci/pci.c b/arch/loongarch/pci/pci.c
> > index 5bc9627a6cf9..d9fc5d520b37 100644
> > --- a/arch/loongarch/pci/pci.c
> > +++ b/arch/loongarch/pci/pci.c
> > @@ -50,11 +50,11 @@ static int __init pcibios_init(void)
> >        */
> >       lsize = cpu_last_level_cache_line_size();
> >
> > -     BUG_ON(!lsize);
> > +     if (lsize) {
> > +             pci_dfl_cache_line_size = lsize >> 2;
> >
> > -     pci_dfl_cache_line_size = lsize >> 2;
> > -
> > -     pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
> > +             pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
> > +     }
> >
> >       return 0;
> >   }
> Mind adding a few words about why this is no longer considered a BUG and
> why functionality isn't adversely affected by the change?
Yes, you are right, so I split this part into a separate patch.
https://lore.kernel.org/loongarch/20251120082039.2293136-1-chenhuacai@loongson.cn/T/#u

Huacai
>
> --
> WANG "xen0n" Xuerui
>
> Linux/LoongArch mailing list: https://lore.kernel.org/loongarch/
>